View M30L0R7000XX_1269307.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

M30L0R7000T0 M30L0R7000B0
128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory
FEATURES SUMMARY

SUPPLY VOLTAGE - VDD = 1.7V to 2.0V for program, erase and read - VDDQ = 1.7V to 2.0V for I/O Buffers - VPP = 9V for fast program (12V tolerant) SYNCHRONOUS / ASYNCHRONOUS READ - Synchronous Burst Read mode: 54MHz - Asynchronous Page Read mode - Random Access: 85ns SYNCHRONOUS BURST READ SUSPEND PROGRAMMING TIME - 10s typical Word program time using Buffer Program MEMORY ORGANIZATION - Multiple Bank Memory Array: 8 Mbit Banks - Parameter Blocks (Top or Bottom location) DUAL OPERATIONS - program/erase in one Bank while read in others - No delay between read and write operations BLOCK LOCKING - All blocks locked at power-up - Any combination of blocks can be locked with zero latency - WP for Block Lock-Down - Absolute Write Protection with VPP = VSS SECURITY - 64 bit unique device number - 2112 bit user programmable OTP Cells COMMON FLASH INTERFACE (CFI) 100,000 PROGRAM/ERASE CYCLES per BLOCK
Figure 1. Package
FBGA
TFBGA88 (ZAQ) 8 x 10mm
ELECTRONIC SIGNATURE - Manufacturer Code: 20h - Top Device Code: 88C4h. - Bottom Device Code: 88C5h PACKAGE - Compliant with Lead-Free Soldering Processes - Lead-Free Versions
December 2004
1/83
M30L0R7000T0, M30L0R7000B0
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Table 1. Figure 3. Table 2. Figure 4. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Address Inputs (A0-A22). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Reset (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Latch Enable (L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Clock (K).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Wait (WAIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VDD Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VDDQ Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VPP Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VSSQ Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Address Latch.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 3. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 4. Command Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Read Array Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Read Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Read CFI Query Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Clear Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
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Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Buffer Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Buffer Enhanced Factory Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Setup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Program and Verify Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Exit Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Protection Register Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Set Configuration Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Block Lock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Block Unlock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Block Lock-Down Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 5. Standard Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 6. Factory Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 7. Electronic Signature Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 5. Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 8. Protection Register Locks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Program/Erase Controller Status Bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Erase Suspend Status Bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Erase Status Bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Program Status Bit (SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 VPP Status Bit (SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Program Suspend Status Bit (SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Block Protection Status Bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Bank Write/Multiple Word Program Status Bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 9. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 CONFIGURATION REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Read Select Bit (CR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 X-Latency Bits (CR13-CR11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Wait Polarity Bit (CR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Data Output Configuration Bit (CR9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Wait Configuration Bit (CR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Burst Type Bit (CR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Valid Clock Edge Bit (CR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Wrap Burst Bit (CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Burst length Bits (CR2-CR0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 10. Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 11. Burst Type Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 6. X-Latency and Data Output Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 7. Wait Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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READ MODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Asynchronous Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Synchronous Burst Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Synchronous Burst Read Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Single Synchronous Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 12. Dual Operations Allowed In Other Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 13. Dual Operations Allowed In Same Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 BLOCK LOCKING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Reading a Block's Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Locked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Unlocked State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Lock-Down State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Locking Operations During Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 14. Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 15. Program, Erase Times and Endurance Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 16. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 17. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 8. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 9. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 18. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 19. DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 20. DC Characteristics - Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 10.Asynchronous Random Access Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 11.Asynchronous Page Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 21. Asynchronous Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 12.Synchronous Burst Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 13.Single Synchronous Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 14.Synchronous Burst Read Suspend AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 15.Clock input AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 22. Synchronous Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 16.Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 23. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 17.Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 24. Write AC Characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 18.Reset and Power-up AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 25. Reset and Power-up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
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PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 19.TFBGA88 8x10mm - 8x10 ball array, 0.8mm pitch, Bottom View Package Outline . . . . 52 Table 26. TFBGA88 8x10mm - 8x10 ball array, 0.8mm pitch, Package Mechanical Data . . . . . . . 52 Figure 20.TFBGA88 Daisy Chain - Package Connections (Top view through package) . . . . . . . . 53 Figure 21.TFBGA88 Daisy Chain - PCB Connection Proposal (Top view through package) . . . . . 54 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 27. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 28. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 APPENDIX A.BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 29. Top Boot Block Addresses, M30L0R7000T0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 30. Bottom Boot Block Addresses, M30L0R7000B0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 APPENDIX B.COMMON FLASH INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 31. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 32. CFI Query Identification String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 33. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 34. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 35. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 36. Protection Register Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 37. Burst Read Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 38. Bank and Erase Block Region Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 39. Bank and Erase Block Region 1 Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 40. Bank and Erase Block Region 2 Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 APPENDIX C.FLOWCHARTS AND PSEUDO CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Figure 22.Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Figure 23.Buffer Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 24.Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 71 Figure 25.Block Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Figure 26.Erase Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . 73 Figure 27.Locking Operations Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 28.Protection Register Program Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . 75 Figure 29.Buffer Enhanced Factory Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . 76 APPENDIX D.COMMAND INTERFACE STATE TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 41. Command Interface States - Modify Table, Next State . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 42. Command Interface States - Modify Table, Next Output State . . . . . . . . . . . . . . . . . . . . 79 Table 43. Command Interface States - Lock Table, Next State . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 44. Command Interface States - Lock Table, Next Output State. . . . . . . . . . . . . . . . . . . . . . 81 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 45. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
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M30L0R7000T0, M30L0R7000B0
SUMMARY DESCRIPTION
The M30L0R7000T0/B0 is a 128 Mbit (8Mbit x16) non-volatile Flash memory that may be erased electrically at block level and programmed in-system on a Word-by-Word basis using a 1.7V to 2.0V VDD supply for the circuitry and a 1.7V to 2.0V VDDQ supply for the Input/Output pins. An optional 9V VPP power supply is provided to speed up factory programming. The device features an asymmetrical block architecture and is based on a multi-level cell technology. M30L0R7000T0/B0 has an array of 131 blocks, and is divided into 8 Mbit banks. There are 15 banks each containing 8 main blocks of 64 KWords, and one parameter bank containing 4 parameter blocks of 16 KWords and 7 main blocks of 64 KWords. The Multiple Bank Architecture allows Dual Operations, while programming or erasing in one bank, read operations are possible in other banks. Only one bank at a time is allowed to be in program or erase mode. It is possible to perform burst reads that cross bank boundaries. The bank architecture is summarized in Table 2., and the memory maps are shown in Figure 4. The Parameter Blocks are located at the top of the memory address space for the M30L0R7000T0, and at the bottom for the M30L0R7000B0. Each block can be erased separately. Erase can be suspended, in order to perform program in any other block, and then resumed. Program can be suspended to read data in any other block and then resumed. Each block can be programmed and erased over 100,000 cycles using the supply voltage VDD. There is a Buffer Enhanced Factory programming command available to speed up programming. Program and erase commands are written to the Command Interface of the memory. An internal Program/Erase Controller takes care of the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified in the Status Register. The command set required to control the memory is consistent with JEDEC standards. The device supports Synchronous Burst Read and Asynchronous Read from all blocks of the memory array; at power-up the device is configured for Asynchronous Read. In Synchronous Burst Read mode, data is output on each clock cycle at frequencies of up to 54MHz. The Synchronous Burst Read operation can be suspended and resumed. The device features an Automatic Standby mode. When the bus is inactive during Asynchronous Read operations, the device automatically switches to the Automatic Standby mode. In this condition the power consumption is reduced to the standby value and the outputs are still driven. The M30L0R7000T0/B0 features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. All blocks have three levels of protection. They can be locked and locked-down individually preventing any accidental programming or erasure. There is an additional hardware protection against program and erase. When VPP VPPLK all blocks are protected against program or erase. All blocks are locked at powerup. The device includes 17 Protection Registers and 2 Protection Register locks, one for the first Protection Register and the other for the 16 One-TimeProgrammable (OTP) Protection Registers of 128 bits each. The first Protection Register is divided into two segments: a 64 bit segment containing a unique device number written by ST, and a 64 bit segment One-Time-Programmable (OTP) by the user. The user programmable segment can be permanently protected. Figure 5., shows the Protection Register Memory Map. The memory is available in a TFBGA88, 8 x 10mm, 0.8mm pitch package. In addition to the standard version, the packages are also available in Lead-free version, in compliance with JEDEC Std J-STD-020B, the ST ECOPACK 7191395 Specification, and the RoHS (Restriction of Hazardous Substances) directive. All packages are compliant with Lead-free soldering processes. The memory is supplied with all the bits erased (set to '1').
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M30L0R7000T0, M30L0R7000B0
Figure 2. Logic Diagram Table 1. Signal Names
A0-A22 DQ0-DQ15 Address Inputs Data Input/Outputs, Command Inputs Chip Enable Output Enable Write Enable Reset Write Protect Clock Latch Enable Wait Supply Voltage Supply Voltage for Input/Output Buffers Optional Supply Voltage for Fast Program & Erase Ground Ground Input/Output Supply Not Connected Internally Do Not Use
VDD VDDQ VPP 23 A0-A22 W E G RP WP L K M30L0R7000T0 M30L0R7000TB WAIT 16 DQ0-DQ15
E G W RP WP K L WAIT VDD VDDQ VPP
AI08337
VSS
VSSQ
VSS VSSQ NC DU
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M30L0R7000T0, M30L0R7000B0
Figure 3. TFBGA Connections (Top view through package)
1 2 3 4 5 6 7 8
A
DU
DU
DU
DU
B
A4
A18
A19
VSS
VDD
NC
A21
A11
C
A5
NC
NC
VSS
NC
K
A22
A12
D
A3
A17
NC
VPP
NC
NC
A9
A13
E
A2
A7
NC
WP
L
A20
A10
A15
F
A1
A6
NC
RP
W
A8
A14
A16
G
A0
DQ8
DQ2
DQ10
DQ5
DQ13
WAIT
NC
H
NC
DQ0
DQ1
DQ3
DQ12
DQ14
DQ7
NC
J
NC
G
DQ9
DQ11
DQ4
DQ6
DQ15
VDDQ
K
E
NC
NC
NC
NC
NC
VDDQ
NC
L
VSS
VSS
VDDQ
VDD
VSS
VSS
VSS
VSS
M
DU
DU
DU
DU
AI08303
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M30L0R7000T0, M30L0R7000B0
Table 2. Bank Architecture
Number Parameter Bank Bank 1 Bank 2 Bank 3 ---Bank Size 8 Mbits 8 Mbits 8 Mbits 8 Mbits ---Parameter Blocks 4 blocks of 16 KWords ---Main Blocks 7 blocks of 64 KWords 8 blocks of 64 KWords 8 blocks of 64 KWords 8 blocks of 64 KWords ---8 blocks of 64 KWords 8 blocks of 64 KWords
M30L0R7000B0 - Bottom Boot Block Address lines A22-A0 000000h 003FFFh 00C000h 00FFFFh 010000h 01FFFFh 070000h 07FFFFh 080000h 08FFFFh Bank 1 0F0000h 0FFFFFh 100000h 10FFFFh Bank 2 170000h 17FFFFh 180000h 18FFFFh Bank 3 1F0000h 1FFFFFh 7 Main Blocks 64 KWord 16 KWord 4 Parameter Blocks 16 KWord Bank 15 7F0000h 7FFFFFh 64 KWord 780000h 78FFFFh 64 KWord 8 Main Blocks 64 KWord 64 KWord 64 KWord 8 Main Blocks 64 KWord 64 KWord 8 Main Blocks 16 KWord 4 Parameter Blocks 16 KWord 64 KWord 7 Main Blocks 64 KWord 64 KWord 8 Main Blocks
Bank 14 Bank 15
8 Mbits 8 Mbits
-
Figure 4. Memory Map
M30L0R7000T0 - Top Boot Block Address lines A22-A0 000000h 00FFFFh Bank 15 070000h 07FFFFh 64 KWord 64 KWord 8 Main Blocks Parameter Bank
600000h 60FFFFh Bank 3 670000h 67FFFFh 680000h 68FFFFh Bank 2 6F0000h 6FFFFFh 700000h 70FFFFh Bank 1 770000h 77FFFFh 780000h 78FFFFh 7E0000h 7EFFFFh 7F0000h 7F3FFFh 7FC000h 7FFFFFh
64 KWord 8 Main Blocks 64 KWord 64 KWord 8 Main Blocks 64 KWord 64 KWord 8 Main Blocks 64 KWord 64 KWord
Parameter Bank
AI08338
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M30L0R7000T0, M30L0R7000B0
SIGNAL DESCRIPTIONS
See Figure 2., Logic Diagram and Table 1., Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A0-A22). The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine. Data Input/Output (DQ0-DQ15). The Data I/O outputs the data stored at the selected address during a Bus Read operation or inputs a command or the data to be programmed during a Bus Write operation. Chip Enable (E). The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is at VILand Reset is at VIH the device is in active mode. When Chip Enable is at VIH the memory is deselected, the outputs are high impedance and the power consumption is reduced to the stand-by level. Output Enable (G). The Output Enable controls data outputs during the Bus Read operation of the memory. Write Enable (W). The Write Enable controls the Bus Write operation of the memory's Command Interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first. Write Protect (WP). Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is at VIL, the LockDown is enabled and the protection status of the Locked-Down blocks cannot be changed. When Write Protect is at VIH, the Lock-Down is disabled and the Locked-Down blocks can be locked or unlocked. (refer to Table 14., Lock Status). Reset (RP). The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in reset mode: the outputs are high impedance and the current consumption is reduced to the Reset Supply Current IDD2. Refer to Table 19., DC Characteristics - Currents, for the value of IDD2. After Reset all blocks are in the Locked state and the Configuration Register is reset. When Reset is at VIH, the device is in normal operation. Exiting reset mode the device enters asynchronous read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs. The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied to VRPH (refer to Table 20., DC Characteristics - Voltages). Latch Enable (L). Latch Enable latches the address bits on its rising edge. The address latch is transparent when Latch Enable is at V IL and it is inhibited when Latch Enable is at V IH . Latch Enable can be kept Low (also at board level) when the Latch Enable function is not required or supported. Clock (K). The clock input synchronizes the memory to the microcontroller during synchronous read operations; the address is latched on a Clock edge (rising or falling, according to the configuration settings) when Latch Enable is at VIL. Clock is ignored during asynchronous read and in write operations. Wait (WAIT). Wait is an output signal used during synchronous read to indicate whether the data on the output bus are valid. This output is high impedance when Chip Enable is at VIH, Output Enable is at VIH, or Reset is at VIL. It can be configured to be active during the wait cycle or one clock cycle in advance. VDD Supply Voltage . VDD provides the power supply to the internal core of the memory device. It is the main power supply for all operations (Read, Program and Erase). VDDQ Supply Voltage. VDDQ provides the power supply to the I/O pins and enables all Outputs to be powered independently from VDD. VDDQ can be tied to VDD or can use a separate supply. VPP Program Supply Voltage. VPP is both a control input and a power supply pin. The two functions are selected by the voltage range applied to the pin. If VPP is kept in a low voltage range (0V to VDDQ) VPP is seen as a control input. In this case a voltage lower than VPPLK gives an absolute protection against program or erase, while VPP > VPP1 enables these functions (see Tables 19 and 20, DC Characteristics for the relevant values). VPP is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. If VPP is in the range of VPPH it acts as a power supply pin. In this condition VPP must be stable until the Program/Erase algorithm is completed. VSS Ground. VSS ground is the reference for the core supply. It must be connected to the system ground. VSSQ Ground. VSSQ ground is the reference for the input/output circuitry driven by VDDQ. VSSQ must be connected to VSS Note: Each device in a system should have VDD, VDDQ and VPP decoupled with a 0.1F ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors
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M30L0R7000T0, M30L0R7000B0
should be as close as possible to the package). See Figure 9., AC Measurement Load Circuit. The PCB trace widths should be sufficient to carry the required VPP program and erase currents.
BUS OPERATIONS
There are six standard bus operations that control the device. These are Bus Read, Bus Write, Address Latch, Output Disable, Standby and Reset. See Table 3., Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect Bus Write operations. Bus Read. Bus Read operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register and the Common Flash Interface. Both Chip Enable and Output Enable must be at VIL in order to perform a read operation. The Chip Enable input should be used to enable the device. Output Enable should be used to gate data onto the output. The data read depends on the previous command written to the memory (see Command Interface section). See Figures 10, 11, 12 and 13 Read AC Waveforms, and Tables 21 and 22 Read AC Characteristics, for details of when the output becomes valid. Bus Write. Bus Write operations write Commands to the memory or latch Input Data to be programmed. A bus write operation is initiated when Chip Enable and Write Enable are at VIL with Output Enable at VIH. Commands, Input Data and Addresses are latched on the rising edge of Write Enable or Chip Enable, whichever occurs first. The addresses can also be latched prior to the write operation by toggling Latch Enable. In this case Table 3. Bus Operations
Operation Bus Read Bus Write Address Latch Output Disable Standby Reset
Note: 1. 2. 3. 4.
the Latch Enable should be tied to VIH during the bus write operation. See Figures 16 and 17, Write AC Waveforms, and Tables 23 and 24, Write AC Characteristics, for details of the timing requirements. Address Latch. Address latch operations input valid addresses. Both Chip enable and Latch Enable must be at VIL during address latch operations. The addresses are latched on the rising edge of Latch Enable. Output Disable. The outputs are high impedance when the Output Enable is at VIH. Standby. Standby disables most of the internal circuitry allowing a substantial reduction of the current consumption. The memory is in standby when Chip Enable and Reset are at VIH. The power consumption is reduced to the standby level IDD4 and the outputs are set to high impedance, independently from the Output Enable or Write Enable inputs. If Chip Enable switches to VIH during a program or erase operation, the device enters Standby mode when finished. Reset. During Reset mode the memory is deselected and the outputs are high impedance. The memory is in Reset mode when Reset is at VIL. The power consumption is reduced to the Standby level, independently from the Chip Enable, Output Enable or Write Enable inputs. If Reset is pulled to VSS during a Program or Erase, this operation is aborted and the memory content is no longer valid.
E VIL VIL VIL VIL VIH X
G VIL VIH X VIH X X
W VIH VIL VIH VIH X X
L VIL(2) VIL(2) VIL X X X
RP VIH VIH VIH VIH VIH VIL
WAIT(4)
DQ15-DQ0 Data Output Data Input Data Output or Hi-Z (3)
Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z Hi-Z
X = Don't care. L can be tied to VIH if the valid address has been previously latched. Depends on G. WAIT signal polarity is configured using the Set Configuration Register command.
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M30L0R7000T0, M30L0R7000B0
COMMAND INTERFACE
All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. An internal Program/Erase Controller handles all timings and verifies the correct execution of the program and erase commands. The Program/Erase Controller provides a Status Register whose output may be read at any time to monitor the progress or the result of the operation. The Command Interface is reset to read mode when power is first applied, when exiting from Reset or whenever VDD is lower than VLKO. Command sequences must be followed exactly. Any invalid combination of commands will be ignored. Refer to Table 4., Command Codes, Table 5., Standard Commands, and Table 6., Factory Program Command, for a summary of the Command Interface. Table 4. Command Codes
Hex Code 01h 03h 10h 20h 2Fh 40h 50h 60h 70h 80h 90h 98h B0h C0h D0h E8h FFh Command Block Lock Confirm Set Configuration Register Confirm Alternative Program Setup Block Erase Setup Block Lock-Down Confirm Program Setup Clear Status Register Block Lock Setup, Block Unlock Setup, Block Lock Down Setup and Set Configuration Register Setup Read Status Register Buffer Enhanced Factory Program Read Electronic Signature Read CFI Query Program/Erase Suspend Protection Register Program Program/Erase Resume, Block Erase Confirm, Block Unlock Confirm or Buffer Program Confirm Buffer Program Read Array
Read Array Command The Read Array command returns the addressed bank to Read Array mode. One Bus Write cycle is required to issue the Read Array command. Once a bank is in Read Array mode, subsequent read operations will output the data from the memory array. A Read Array command can be issued to any banks while programming or erasing in another bank. If the Read Array command is issued to a bank currently executing a program or erase operation, the bank will return to Read Array mode but the program or erase operation will continue, however the data output from the bank is not guaranteed until the program or erase operation has finished. The read modes of other banks are not affected. Read Status Register Command The device contains a Status Register that is used to monitor program or erase operations. The Read Status Register command is used to read the contents of the Status Register for the addressed bank. One Bus Write cycle is required to issue the Read Status Register command. Once a bank is in Read Status Register mode, subsequent read operations will output the contents of the Status Register. The Status Register data is latched on the falling edge of the Chip Enable or Output Enable signals. Either Chip Enable or Output Enable must be toggled to update the Status Register data The Read Status Register command can be issued at any time, even during program or erase operations. The Read Status Register command will only change the read mode of the addressed bank. The read modes of other banks are not affected. Only Asynchronous Read and Single Synchronous Read operations should be used to read the Status Register. A Read Array command is required to return the bank to Read Array mode. See Table 9. for the description of the Status Register Bits. Read Electronic Signature Command The Read Electronic Signature command is used to read the Manufacturer and Device Codes, the Lock Status of the addressed bank, the Protection Register, and the Configuration Register. One Bus Write cycle is required to issue the Read Electronic Signature command. Once a bank is in Read Electronic Signature mode, subsequent read operations in the same bank will output the Manufacturer Code, the Device Code, the Lock
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M30L0R7000T0, M30L0R7000B0
Status of the addressed bank, the Protection Register, or the Configuration Register (see Table 7.). The Read Electronic Signature command can be issued at any time, even during program or erase operations, except during Protection Register Program operations. If a Read Electronic Signature command is issued to a bank that is executing a program or erase operation the bank will go into Read Electronic Signature mode. Subsequent Bus Read cycles will output the Electronic Signature data and the Program/Erase controller will continue to program or erase in the background. The Read Electronic Signature command will only change the read mode of the addressed bank. The read modes of other banks are not affected. Only Asynchronous Read and Single Synchronous Read operations should be used to read the Electronic Signature. A Read Array command is required to return the bank to Read Array mode. Read CFI Query Command The Read CFI Query command is used to read data from the Common Flash Interface (CFI). One Bus Write cycle is required to issue the Read CFI Query command. Once a bank is in Read CFI Query mode, subsequent Bus Read operations in the same bank read from the Common Flash Interface. The Read CFI Query command can be issued at any time, even during program or erase operations. If a Read CFI Query command is issued to a bank that is executing a program or erase operation the bank will go into Read CFI Query mode. Subsequent Bus Read cycles will output the CFI data and the Program/Erase controller will continue to program or erase in the background. The Read CFI Query command will only change the read mode of the addressed bank. The read modes of other banks are not affected. Only Asynchronous Read and Single Synchronous Read operations should be used to read from the CFI. A Read Array command is required to return the bank to Read Array mode. See APPENDIX B., COMMON FLASH INTERFACE, Tables 31, 32, 33, 34, 35, 37, 38, 39 and 40 for details on the information contained in the Common Flash Interface memory area. Clear Status Register Command The Clear Status Register command can be used to reset (set to `0') all error bits (SR1, 3, 4 and 5) in the Status Register. One Bus Write cycle is required to issue the Clear Status Register command. The Clear Status Register command does not change the read mode of the addressed bank. The error bits in the Status Register do not automatically return to `0' when a new command is issued. The error bits in the Status Register should be cleared before attempting a new program or erase command. Block Erase Command The Block Erase command is used to erase a block. It sets all the bits within the selected block to '1'. All previous data in the block is lost. If the block is protected then the erase operation will abort, the data in the block will not be changed and the Status Register will output the error. Two Bus Write cycles are required to issue the command. The first bus cycle sets up the Block Erase command. The second latches the block address and starts the Program/Erase Controller. If the second bus cycle is not the Block Erase Confirm code, Status Register bits SR4 and SR5 are set and the command is aborted. Once the command is issued the bank enters Read Status Register mode and any read operation within the addressed bank will output the contents of the Status Register. A Read Array command is required to return the bank to Read Array mode. During Block Erase operations the bank containing the block being erased will only accept the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/ Erase Suspend command, all other commands will be ignored. The Block Erase operation aborts if Reset, RP, goes to VIL. As data integrity cannot be guaranteed when the Block Erase operation is aborted, the block must be erased again. Refer to Dual Operations section for detailed information about simultaneous operations allowed in banks not being erased. Typical Erase times are given in Table 15., Program, Erase Times and Endurance Cycles. See APPENDIX C., Figure 25., Block Erase Flowchart and Pseudo Code, for a suggested flowchart for using the Block Erase command. Program Command The program command is used to program a single Word to the memory array. Two Bus Write cycles are required to issue the Program Command. The first bus cycle sets up the Program command.
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M30L0R7000T0, M30L0R7000B0
The second latches the address and data to be programmed and starts the Program/Erase Controller. Once the programming has started, read operations in the bank being programmed output the Status Register content. During a Program operation, the bank containing the Word being programmed will only accept the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/ Erase Suspend command, all other commands will be ignored. A Read Array command is required to return the bank to Read Array mode. Refer to Dual Operations section for detailed information about simultaneous operations allowed in banks not being programmed. Typical Program times are given in Table 15., Program, Erase Times and Endurance Cycles. The Program operation aborts if Reset, RP, goes to VIL. As data integrity cannot be guaranteed when the Program operation is aborted, the Word must be reprogrammed. See APPENDIX C., Figure 22., Program Flowchart and Pseudo Code, for the flowchart for using the Program command. Buffer Program Command The Buffer Program Command makes use of the device's 32-Word Write Buffer to speed up programming. Up to 32 Words can be loaded into the Write Buffer. The Buffer Program command dramatically reduces in-system programming time compared to the standard non-buffered Program command. Four successive steps are required to issue the Buffer Program command. 1. The first Bus Write cycle sets up the Buffer Program command. The setup code can be addressed to any location within the targeted block. After the first Bus Write cycle, read operations in the bank will output the contents of the Status Register. Status Register bit SR7 should be read to check that the buffer is available (SR7 = 1). If the buffer is not available (SR7 = 0), re-issue the Buffer Program command to update the Status Register contents. 2. The second Bus Write cycle sets up the number of Words to be programmed. Value n is written to the same block address, where n+1 is the number of Words to be programmed. 3. Use n+1 Bus Write cycles to load the address and data for each Word into the Write Buffer. Addresses must lie within the range from the start address to the start address + n.
Optimum performance is obtained when the start address corresponds to a 32 Word boundary. If the start address is not aligned to a 32 word boundary, the total programming time is doubled 4. The final Bus Write cycle confirms the Buffer Program command and starts the program operation. All the addresses used in the Buffer Program operation must lie within the same block. Invalid address combinations or failing to follow the correct sequence of Bus Write cycles will set an error in the Status Register and abort the operation without affecting the data in the memory array. If the Status Register bits SR4 and SR5 are set to '1', the Buffer Program Command is not accepted. Clear the Status Register before re-issuing the command. If the block being programmed is protected an error will be set in the Status Register and the operation will abort without affecting the data in the memory array. During Buffer Program operations the bank being programmed will only accept the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase Suspend command, all other commands will be ignored. Refer to Dual Operations section for detailed information about simultaneous operations allowed in banks not being programmed. See Appendix C, figure 27, Buffer Program Flowchart and Pseudo Code, for a suggested flowchart on using the Buffer Program command. Buffer Enhanced Factory Program Command The Buffer Enhanced Factory Program command has been specially developed to speed up programming in manufacturing environments where the programming time is critical. It is used to program one or more Write Buffer(s) of 32 Words to a block. Once the device enters Buffer Enhanced Factory Program mode, the Write Buffer can be reloaded any number of times as long as the address remains within the same block. Only one block can be programmed at a time. The use of the Buffer Enhanced Factory Program command requires certain operating conditions: VPP must be set to VPPH VDD must be within operating range Ambient temperature, TA must be 25C 5C The targeted block must be unlocked The start address must be aligned with the start of a 32 Word buffer boundary
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The address must remain the Start Address throughout programming. Dual operations are not supported during the Buffer Enhanced Factory Program operation and the command cannot be suspended. The Buffer Enhanced Factory Program Command consists of three phases: the Setup Phase, the Program and Verify Phase, and the Exit Phase, Please refer to Table 7. Factory Program Commands for detail information. Refer to Table 6., Factory Program Command, and Figure 29., Buffer Enhanced Factory Program Flowchart and Pseudo Code. Setup Phase. The Buffer Enhanced Factory Program command requires two Bus Write cycles to initiate the command. The first Bus Write cycle sets up the Buffer Enhanced Factory Program command. The second Bus Write cycle confirms the command. After the confirm command is issued, read operations output the contents of the Status Register. The read Status Register command must not be issued as it will be interpreted as data to program. The Status Register P/E.C. Bit SR7 should be read to check that the P/E.C. is ready to proceed to the next phase. If an error is detected, SR4 goes high (set to `1') and the Buffer Enhanced Factory Program operation is terminated. See Status Register section for details on the error. Program and Verify Phase. The Program and Verify Phase requires 32 cycles to program the 32 Words to the Write Buffer. The data is stored sequentially, starting at the first address of the Write Buffer, until the Write Buffer is full (32 Words). To program less than 32 Words, the remaining Words should be programmed with FFFFh. Three successive steps are required to issue and execute the Program and Verify Phase of the command. 1. Use one Bus Write operation to latch the Start Address and the first Word to be programmed. The Status Register Bank Write Status bit SR0 should be read to check that the P/E.C. is ready for the next Word. 2. Each subsequent Word to be programmed is latched with a new Bus Write operation. The address must remain the Start Address as the P/E.C. increments the address location.If any address that is not in the same block as the Start Address is given, the Program and Verify Phase terminates. Status Register bit SR0 should be read between each Bus Write cycle to check that the P/E.C. is ready for the next Word.
3. Once the Write Buffer is full, the data is programmed sequentially to the memory array. After the program operation the device automatically verifies the data and reprograms if necessary. The Program and Verify phase can be repeated, without re-issuing the command, to program additional 32 Word locations as long as the address remains in the same block. 4. Finally, after all Words, or the entire block have been programmed, write one Bus Write operation to any address outside the block containing the Start Address, to terminate Program and Verify Phase. Status Register bit SR0 must be checked to determine whether the program operation is finished. The Status Register may be checked for errors at any time but it must be checked after the entire block has been programmed. Exit Phase. Status Register P/E.C. bit SR7 set to `1' indicates that the device has exited the Buffer Enhanced Factory Program operation and returned to Read Status Register mode. A full Status Register check should be done to ensure that the block has been successfully programmed. See the section on the Status Register for more details. For optimum performance the Buffer Enhanced Factory Program command should be limited to a maximum of 100 program/erase cycles per block. If this limit is exceeded the internal algorithm will continue to work properly but some degradation in performance is possible. Typical program times are given in Table 15.. See APPENDIX C., Figure 29., Buffer Enhanced Factory Program Flowchart and Pseudo Code, for a suggested flowchart on using the Buffer Enhanced Factory Program command. Program/Erase Suspend Command The Program/Erase Suspend command is used to pause a Program or Block Erase operation. The command can be addressed to any bank. The Program/Erase Resume command is required to restart the suspended operation. One bus write cycle is required to issue the Program/Erase Suspend command. Once the Program/Erase Controller has paused bits SR7, SR6 and/ or SR2 of the Status Register will be set to `1'. The following commands are accepted during Program/Erase Suspend: - Program/Erase Resume - Read Array (data from erase-suspended block or program-suspended Word is not valid) - Read Status Register - Read Electronic Signature
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- Read CFI Query. Additionally, if the suspended operation was erase then the following commands are also accepted: - Clear Status Register - Program (except in erase-suspended block) - Block Lock - Block Lock-Down - Block Unlock. During an erase suspend the block being erased can be protected by issuing the Block Lock or Block Lock-Down commands. When the Program/ Erase Resume command is issued the operation will complete. It is possible to accumulate multiple suspend operations. For example: suspend an erase operation, start a program operation, suspend the program operation, then read the array. If a Program command is issued during a Block Erase Suspend, the erase operation cannot be resumed until the program operation has completed. The Program/Erase Suspend command does not change the read mode of the banks. If the suspended bank was in Read Status Register, Read Electronic signature or Read CFI Query mode the bank remains in that mode and outputs the corresponding data. Refer to Dual Operations section for detailed information about simultaneous operations allowed during Program/Erase Suspend. During a Program/Erase Suspend, the device can be placed in standby mode by taking Chip Enable to VIH. Program/erase is aborted if Reset, RP, goes to VIL. See APPENDIX C., Figure 24., Program Suspend & Resume Flowchart and Pseudo Code, and Figure 26., Erase Suspend & Resume Flowchart and Pseudo Code, for flowcharts for using the Program/Erase Suspend command. Program/Erase Resume Command The Program/Erase Resume command is used to restart the program or erase operation suspended by the Program/Erase Suspend command. One Bus Write cycle is required to issue the command. The command can be issued to any address. The Program/Erase Resume command does not change the read mode of the banks. If the suspended bank was in Read Status Register, Read Electronic signature or Read CFI Query mode the bank remains in that mode and outputs the corresponding data. If a Program command is issued during a Block Erase Suspend, then the erase cannot be resumed until the program operation has completed. See APPENDIX C., Figure 24., Program Suspend & Resume Flowchart and Pseudo Code, and Figure 26., Erase Suspend & Resume Flowchart and Pseudo Code, for flowcharts for using the Program/Erase Resume command. Protection Register Program Command The Protection Register Program command is used to program the user One-Time-Programmable (OTP) segments of the Protection Register and the two Protection Register Locks. The device features 16 OTP segments of 128 bits and one OTP segment of 64 bits, as shown in Figure 5., Protection Register Memory Map. The segments are programmed one Word at a time. When shipped all bits in the segment are set to `1'. The user can only program the bits to `0'. Two Bus Write cycles are required to issue the Protection Register Program command. The first bus cycle sets up the Protection Register Program command. The second latches the address and data to be programmed to the Protection Register and starts the Program/Erase Controller. Read operations to the bank being programmed output the Status Register content after the program operation has started. Attempting to program a previously protected Protection Register will result in a Status Register error. The Protection Register Program cannot be suspended. The two Protection Register Locks are used to protect the OTP segments from further modification. The protection of the OTP segments is not reversible. Refer to Figure 5., Protection Register Memory Map, and Table 8., Protection Register Locks, for details on the Lock bits. See APPENDIX C., Figure 28., Protection Register Program Flowchart and Pseudo Code, for a flowchart for using the Protection Register Program command. Set Configuration Register Command The Set Configuration Register command is used to write a new value to the Configuration Register. Two Bus Write cycles are required to issue the Set Configuration Register command. The first cycle sets up the Set Configuration Register command and the address corresponding to the Configuration Register content. The second cycle writes the Configuration Register data and the confirm command. The Configuration Register data must be written as an address during the bus write cycles, that is
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A0 = CR0, A1 = CR1, ..., A15 = CR15. Addresses A16- A22 are ignored. Once the Set Configuration Register command has been issued, read operations will output the array contents. The Read Electronic Signature command is required to read the updated contents of the Configuration Register. Block Lock Command The Block Lock command is used to lock a block and prevent program or erase operations from changing the data in it. All blocks are locked after power-up or reset. Two Bus Write cycles are required to issue the Block Lock command. The first bus cycle sets up the Block Lock command. The second Bus Write cycle latches the block address and locks the block. The lock status can be monitored for each block using the Read Electronic Signature command. Table 14. shows the Lock Status after issuing a Block Lock command. Once set, the Block Lock bits remain set until a hardware reset or power-down/power-up. They are cleared by a Block Unlock command. Refer to the section, Block Locking, for a detailed explanation. See APPENDIX C., Figure 27., Locking Operations Flowchart and Pseudo Code, for a flowchart for using the Lock command. Block Unlock Command The Block Unlock command is used to unlock a block, allowing the block to be programmed or erased. Two Bus Write cycles are required to issue the Block Unlock command. The first bus cycle sets up the Block Unlock command. The second Bus Write cycle latches the block address and unlocks the block. The lock status can be monitored for each block using the Read Electronic Signature command. Table 14. shows the protection status after issuing a Block Unlock command. Refer to the section, Block Locking, for a detailed explanation and APPENDIX C., Figure 27., Locking Operations Flowchart and Pseudo Code, for a flowchart for using the Block Unlock command. Block Lock-Down Command The Block Lock-Down command is used to lockdown a locked or unlocked block. A locked-down block cannot be programmed or erased. The lock status of a locked-down block cannot be changed when WP is low, VIL. When WP is high, VIH, the lock-down function is disabled and the locked blocks can be individually unlocked by the Block Unlock command. Two Bus Write cycles are required to issue the Block Lock-Down command. The first bus cycle sets up the Block LockDown command. The second Bus Write cycle latches the block address and locks-down the block. The lock status can be monitored for each block using the Read Electronic Signature command. Locked-Down blocks revert to the locked (and not locked-down) state when the device is reset on power-down. Table 14. shows the Lock Status after issuing a Block Lock-Down command. Refer to the section, Block Locking, for a detailed explanation and APPENDIX C., Figure 27., Locking Operations Flowchart and Pseudo Code, for a flowchart for using the Lock-Down command.
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Table 5. Standard Commands
Cycles Bus Operations 1st Cycle Op. Write Write Write Write Write Write Write Write
Buffer Program n+4
Commands
2nd Cycle Data FFh 70h 90h 98h 50h 20h 40h or 10h E8h PD1 PDn+1 B0h D0h C0h 60h 60h 60h 60h Write Write Write Write Write PRA CRD BA BA BA PRD 03h 01h D0h 2Fh Write Write Write Write Write BA WA BA PA2 X D0h PD n PD2 D0h Op. Read Read Read Read Add WA BKA(2) BKA(2) BKA(2) Data RD SRD ESD QD
Add BKA BKA BKA BKA BKA BKA or BA(3) BKA or WA(3) BA PA1 PAn+1 X X PRA CRD BKA or BA(3) BKA or BA(3) BKA or BA(3)
Read Array Read Status Register Read Electronic Signature Read CFI Query Clear Status Register Block Erase
1+ 1+ 1+ 1+ 1 2
Program
2
Write Write
Program/Erase Suspend Program/Erase Resume Protection Register Program Set Configuration Register Block Lock
1 1 2 2 2
Write Write Write Write Write Write Write
Block Unlock
2
Block Lock-Down
2
Note: 1. X = Don't Care, WA=Word Address in targeted bank, RD=Read Data, SRD=Status Register Data, ESD=Electronic Signature Data, QD=Query Data, BA=Block Address, BKA= Bank Address, PD=Program Data, PRA=Protection Register Address, PRD=Protection Register Data, CRD=Configuration Register Data. 2. Must be same bank as in the first cycle. The signature addresses are listed in Table 7. 3. Any address within the bank can be used. 4. n+1 is the number of Words to be programmed.
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Table 6. Factory Program Command
Cycles Bus Write Operations 1st Add BKA or WA(4) WA1 NOT BA1(2) Data 80h PD1 X 2nd Add WA1 WA1 Data D0h PD2 WA1 PD3 WA1 PD31 WA1 PD32 3rd Add Data Final -1 Add Data Final Add Data Command Phase
Setup Buffer Enhanced Program/ Factory (3)) Program Verify Exit
Note: 1. 2. 3. 4.
2 32 1
WA=Word Address in targeted bank, BKA= Bank Address, PD=Program Data, BA=Block Address, X = Don't Care. WA1 is the Start Address, NOT BA1 = Not Block Address of WA1. The Program/Verify phase can be executed any number of times as long as the data is to be programmed to the same block. Any address within the bank can be used.
Table 7. Electronic Signature Codes
Code Manufacturer Code Top Device Code Bottom Locked Unlocked Block Protection Locked and Locked-Down Unlocked and Locked-Down Configuration Register Protection Register PR0 Lock ST Factory Default Bank Address + 80 OTP Area Permanently Locked Bank Address + 81 Bank Address + 84 Protection Register PR0 Bank Address + 85 Bank Address + 88 Protection Register PR1 through PR16 Lock Protection Registers PR1-PR16
Note: CR = Configuration Register, PRLD = Protection Register Lock Data.
Address (h) Bank Address + 00 Bank Address + 01 Bank Address + 01
Data (h) 0020 88C4 88C5 0001 0000
Block Address + 02 0003 0002 Bank Address + 05 CR 0002 0000 Unique Device Number OTP Area PRLD OTP Area
Bank Address + 89 Bank Address + 8A Bank Address + 109
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Figure 5. Protection Register Memory Map
PROTECTION REGISTERS
109h
PR16
User Programmable OTP
102h
91h
PR1
User Programmable OTP
8Ah Protection Register Lock 89h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
88h 85h 84h
PR0 User Programmable OTP
Unique device number 81h 80h Protection Register Lock 10
AI07563
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Table 8. Protection Register Locks
Lock Description Number Address Bits Bit 0 Lock 1 80h Bit 1 Bits 2 to 15 Bit 0 Bit 1 Bit 2 ---Lock 2 89h preprogrammed to protect Unique Device Number, address 81h to 84h in PR0 protects 64bits of OTP segment, address 85h to 88h in PR0 reserved protects 128bits of OTP segment PR1 protects 128bits of OTP segment PR2 protects 128bits of OTP segment PR3 ---protects 128bits of OTP segment PR14 protects 128bits of OTP segment PR15 protects 128bits of OTP segment PR16
Bit 13 Bit 14 Bit 15
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STATUS REGISTER
The Status Register provides information on the current or previous program or erase operations. Issue a Read Status Register command to read the contents of the Status Register, refer to Read Status Register Command section for more details. To output the contents, the Status Register is latched and updated on the falling edge of the Chip Enable or Output Enable signals and can be read until Chip Enable or Output Enable returns to VIH. The Status Register can only be read using single Asynchronous or Single Synchronous reads. Bus Read operations from any address within the bank, always read the Status Register during program and erase operations. The various bits convey information about the status and any errors of the operation. Bits SR7, SR6, SR2 and SR0 give information on the status of the device and are set and reset by the device. Bits SR5, SR4, SR3 and SR1 give information on errors, they are set by the device but must be reset by issuing a Clear Status Register command or a hardware reset. If an error bit is set to `1' the Status Register should be reset before issuing another command. The bits in the Status Register are summarized in Table 9., Status Register Bits. Refer to Table 9. in conjunction with the following text descriptions. Program/Erase Controller Status Bit (SR7). The Program/Erase Controller Status bit indicates whether the Program/Erase Controller is active or inactive in any bank. When the Program/Erase Controller Status bit is Low (set to `0'), the Program/Erase Controller is active; when the bit is High (set to `1'), the Program/Erase Controller is inactive, and the device is ready to process a new command. The Program/Erase Controller Status bit is Low immediately after a Program/Erase Suspend command is issued until the Program/Erase Controller pauses. After the Program/Erase Controller pauses the bit is High. Erase Suspend Status Bit (SR6). The Erase Suspend Status bit indicates that an erase operation has been suspended in the addressed block. When the Erase Suspend Status bit is High (set to `1'), a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. The Erase Suspend Status bit should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). SR6 is set within the Erase Suspend Latency time of the Program/Erase Suspend command being issued therefore the memory may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is issued the Erase Suspend Status bit returns Low. Erase Status Bit (SR5). The Erase Status bit is used to identify if there was an error during a block or bank erase operation. When the Erase Status bit is High (set to `1'), the Program/Erase Controller has applied the maximum number of pulses to the block or bank and still failed to verify that it has erased correctly. The Erase Status bit should be read once the Program/Erase Controller Status bit is High (Program/ Erase Controller inactive). Once set High, the Erase Status bit must be set Low by a Clear Status Register command or a hardware reset before a new erase command is issued, otherwise the new command will appear to fail. Program Status Bit (SR4). The Program Status bit is used to identify if there was an error during a program operation. The Program Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). When the Program Status bit is High (set to `1'), the Program/Erase Controller has applied the maximum number of pulses to the Word and still failed to verify that it has programmed correctly. Attempting to program a '1' to an already programmed bit while VPP = VPPH will also set the Program Status bit High. If VPP is different from VPPH, SR4 remains Low (set to '0') and the attempt is not shown. Once set High, the Program Status bit must be set Low by a Clear Status Register command or a hardware reset before a new program command is issued, otherwise the new command will appear to fail. VPP Status Bit (SR3). The VPP Status bit is used to identify an invalid voltage on the VPP pin during program and erase operations. The VPP pin is only sampled at the beginning of a program or erase operation. Program and erase operations are not guaranteed if VPP becomes invalid during an operation. When the VPP Status bit is Low (set to `0'), the voltage on the VPP pin was sampled at a valid voltage. when the VPP Status bit is High (set to `1'), the VPP pin has a voltage that is below the VPP Lockout Voltage, VPPLK, the memory is protected and program and erase operations cannot be performed. Once set High, the VPP Status bit must be set Low by a Clear Status Register command or a hardware reset before a new program or erase command is issued, otherwise the new command will appear to fail.
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Program Suspend Status Bit (SR2). The Program Suspend Status bit indicates that a program operation has been suspended in the addressed block. The Program Suspend Status bit should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). When the Program Suspend Status bit is High (set to `1'), a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. SR2 is set within the Program Suspend Latency time of the Program/Erase Suspend command being issued therefore the memory may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is issued the Program Suspend Status bit returns Low. Block Protection Status Bit (SR1). The Block Protection Status bit is used to identify if a Program or Block Erase operation has tried to modify the contents of a locked block. When the Block Protection Status bit is High (set to `1'), a program or erase operation has been attempted on a locked block. Once set High, the Block Protection Status bit must be set Low by a Clear Status Register command or a hardware reset before a new program or erase command is issued, otherwise the new command will appear to fail. Bank Write/Multiple Word Program Status Bit (SR0). The Bank Write Status bit indicates whether the addressed bank is programming or erasing. In Buffer Enhanced Factory Program mode the Multiple Word Program bit shows if the device is ready to accept a new Word to be programmed to the memory array. The Bank Write Status bit should only be considered valid when the Program/Erase Controller Status SR7 is Low (set to `0'). When both the Program/Erase Controller Status bit and the Bank Write Status bit are Low (set to `0'), the addressed bank is executing a program or erase operation. When the Program/Erase Controller Status bit is Low (set to `0') and the Bank Write Status bit is High (set to `1'), a program or erase operation is being executed in a bank other than the one being addressed. In Buffer Enhanced Factory Program mode if Multiple Word Program Status bit is Low (set to `0'), the device is ready for the next Word, if the Multiple Word Program Status bit is High (set to `1') the device is not ready for the next Word. For further details on how to use the Status Register, see the Flowcharts and Pseudocodes provided in APPENDIX C.
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Table 9. Status Register Bits
Bit SR7 Name P/E.C. Status Type Status '0' '1' SR6 Erase Suspend Status Status '0' '1' SR5 Erase Status Error '0' '1' SR4 Program Status Error '0' '1' SR3 VPP Status Error '0' '1' SR2 Program Suspend Status Status '0' '1' SR1 Block Protection Status Error '0' No operation to protected blocks SR7 = `1' Not Allowed '1' SR7 = `0' Bank Write Status Status '0' SR0 Multiple Word Program Status (Buffer Enhanced Factory Program mode) '1' SR7 = `0' the device is NOT ready for the next Word Status SR7 = `1' the device is exiting from BEFP '0' SR7 = `0'
Note: Logic level '1' is High, '0' is Low.
Logic Level '1' Ready Busy Erase Suspended
Definition
Erase In progress or Completed Erase Error Erase Success Program Error Program Success VPP Invalid, Abort VPP OK Program Suspended Program In Progress or Completed Program/Erase on protected Block, Abort
Program or erase operation in a bank other than the addressed bank
SR7 = `1' No Program or erase operation in the device SR7 = `0' Program or erase operation in addressed bank SR7 = `1' Not Allowed
the device is ready for the next Word
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CONFIGURATION REGISTER
The Configuration Register is used to configure the type of bus access that the memory will perform. Refer to Read Modes section for details on read operations. The Configuration Register is set through the Command Interface using the Set Configuration Register command. After a reset or power-up the device is configured for asynchronous read (CR15 = 1). The Configuration Register bits are described in Table 10. They specify the selection of the burst length, burst type, burst X latency and the read operation. Refer to Figures 6 and 7 for examples of synchronous burst configurations. Read Select Bit (CR15) The Read Select bit, CR15, is used to switch between Asynchronous and Synchronous Read operations. When the Read Select bit is set to '1', read operations are asynchronous; when the Read Select bit is set to '0', read operations are synchronous. Synchronous Burst Read is supported in both parameter and main blocks and can be performed across banks. On reset or power-up the Read Select bit is set to '1' for asynchronous access (default). X-Latency Bits (CR13-CR11) The X-Latency bits are used during Synchronous Read operations to set the number of clock cycles between the address being latched and the first data becoming available. For correct operation the X-Latency bits can only assume the values in Table 10., Configuration Register. The correspondence between X-Latency settings and the maximum sustainable frequency must be calculated taking into account some system parameters. Two conditions must be satisfied: 1. Depending on whether tAVK_CPU or tDELAY is supplied either one of the following two equations must be satisfied: (n + 1) tK tAVQV - tAVK_CPU + tQVK_CPU (n + 2) tK tAVQV + tDELAY + tQVK_CPU 2. and also tK > tKQV + tQVK_CPU where n is the chosen X-Latency configuration code tK is the clock period tAVK_CPU is clock to address valid, L Low, or E Low, whichever occurs last tDELAY is address valid, L Low, or E Low to clock, whichever occurs last tQVK_CPU is the data setup time required by the system CPU, tKQV is the clock to data valid time tAVQV is the random access time of the device. Refer to Figure 6., X-Latency and Data Output Configuration Example. Wait Polarity Bit (CR10) The Wait Polarity bit is used to set the polarity of the Wait signal used in Synchronous Burst Read mode. During Synchronous Burst Read mode the Wait signal indicates whether the data output are valid or a WAIT state must be inserted. When the Wait Polarity bit is set to `0' the Wait signal is active Low. When the Wait Polarity bit is set to `1' the Wait signal is active High (default). Data Output Configuration Bit (CR9) The Data Output Configuration bit is used to configure the output to remain valid for either one or two clock cycles during synchronous mode. When the Data Output Configuration Bit is '0' the output data is valid for one clock cycle, when the Data Output Configuration Bit is '1' the output data is valid for two clock cycles. The Data Output Configuration must be configured using the following condition: tK > tKQV + tQVK_CPU where tK is the clock period tQVK_CPU is the data setup time required by the system CPU tKQV is the clock to data valid time. If this condition is not satisfied, the Data Output Configuration bit should be set to `1' (two clock cycles). Refer to Figure 6., X-Latency and Data Output Configuration Example. Wait Configuration Bit (CR8) The Wait Configuration bit is used to control the timing of the Wait output pin, WAIT, in Synchronous Burst Read mode. When WAIT is asserted, Data is Not Valid and when WAIT is de-asserted, Data is Valid. When the Wait Configuration bit is Low (set to '0') the Wait output pin is asserted during the wait state. When the Wait Configuration bit is High (set to '1') (default) the Wait output pin is asserted one clock cycle before the wait state. Burst Type Bit (CR7) The Burst Type bit determines the sequence of addresses read during Synchronous Burst Reads. The Burst Type bit is High (set to '1'), as the memory outputs from sequential addresses only.
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See Table 11., Burst Type Definition, for the sequence of addresses output from a given starting address in sequential mode. Valid Clock Edge Bit (CR6) The Valid Clock Edge bit, CR6, is used to configure the active edge of the Clock, K, during synchronous read operations. When the Valid Clock Edge bit is Low (set to '0') the falling edge of the Clock is the active edge. When the Valid Clock Edge bit is High (set to '1') the rising edge of the Clock is the active edge. Wrap Burst Bit (CR3) The Wrap Burst bit, CR3, is used to select between wrap and no wrap. Synchronous burst reads can be confined inside the 4, 8 or 16 Word boundary (wrap) or overcome the boundary (no wrap). When the Wrap Burst bit is Low (set to `0') the burst read wraps. When it is High (set to `1') the burst read does not wrap. Burst length Bits (CR2-CR0) The Burst Length bits are used to set the number of Words to be output during a Synchronous Burst Read operation as result of a single address latch cycle. They can be set for 4 Words, 8 Words, 16 Words or continuous burst, where all the Words are read sequentially. In continuous burst mode the burst sequence can cross bank boundaries. In continuous burst mode, in 4, 8 or 16 Words nowrap, depending on the starting address, the device asserts the WAIT signal to indicate that a delay is necessary before the data is output. If the starting address is aligned to a 4 Word boundary no wait states are needed and the WAIT output is not asserted. If the starting address is shifted by 1, 2 or 3 positions from the four word boundary, WAIT will be asserted for 1, 2 or 3 clock cycles when the burst sequence crosses the first 16 Word boundary, to indicate that the device needs an internal delay to read the successive Words in the array. WAIT will be asserted only once during a continuous burst access. See also Table 11., Burst Type Definition. CR14, CR5 and CR4 are reserved for future use.
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Table 10. Configuration Register
Bit CR15 CR14 010 011 100 CR13-CR11 X-Latency 101 111 5 clock latency Reserved (default) Description 0 Read Select 1 Asynchronous Read (Default at power-on) Reserved 2 clock latency 3 clock latency 4 clock latency Value Synchronous Read Description
Other configurations reserved 0 CR10 Wait Polarity 1 CR9 Data Output Configuration Wait Configuration 1 0 CR7 Burst Type 1 0 CR6 CR5-CR4 0 CR3 Wrap Burst 1 001 010 CR2-CR0 Burst Length 011 111 16 Words Continuous (default) No Wrap (default) 4 Words 8 Words Valid Clock Edge 1 Rising Clock edge (default) Reserved Wrap Sequential (default) Falling Clock edge WAIT is active one data cycle before wait state (default) Reserved 0 1 0 CR8 WAIT is active high (default) Data held for one clock cycle Data held for two clock cycles (default) WAIT is active during wait state WAIT is active Low
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Table 11. Burst Type Definition
Mode Start Add 0 1 2 3 Wrap ... 7 ... 12 13 14 15 0 1 2 0-1-2-3 1-2-3-4 2-3-4-5 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9... 0-1-2-3-4-5-6-7-8-9-10-11-12-1314-15 1-2-3-4-5-6-7-8-9-10-11-12-13-1415-WAIT-16 2-3-4-5-6-7-8-9-10-11-12-13-1415-WAIT-WAIT-16-17 3-4-5-6-7-8-9-10-11-12-13-14-15WAIT-WAIT-WAIT16-17-18 Same as for Wrap (Wrap /No Wrap has no effect on Continuous Burst) 12-13-14-15-16-17-18... 13-14-15-WAIT-16-17-18... 14-15-WAIT-WAIT-16-17-18.... 15-WAIT-WAIT-WAIT-16-1718... 7-4-5-6 7-0-1-2-3-4-5-6 7-8-9-10-11-12-13-14-15-0-1-2-34-5-6 7-8-9-10-11-12-13-14-15WAIT-WAIT-WAIT-16-17... 4 Words Sequential 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 8 Words Sequential 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 16 Words Sequential 0-1-2-3-4-5-6-7-8-9-10-11-12-1314-15 1-2-3-4-5-6-7-8-9-10-11-12-13-1415-0 2-3-4-5-6-7-8-9-10-11-12-13-1415-0-1 3-4-5-6-7-8-9-10-11-12-13-14-150-1-2 Continuous Burst 0-1-2-3-4-5-6... 1-2-3-4-5-6-7-...15-WAIT-1617-18... 2-3-4-5-6-7...15-WAIT-WAIT16-17-18... 3-4-5-6-7...15-WAIT-WAITWAIT-16-17-18...
3 ... No-wrap 7 ... 12 13 14
3-4-5-6
3-4-5-6-7-8-9-10
7-8-9-10
7-8-9-10-11-12-13-14
7-8-9-10-11-12-13-14-15-WAITWAIT-WAIT-16-17-18-19-20-21-22
12-13-14-15
12-13-14-15-16-1718-19
12-13-14-15-16-17-18-19-20-2122-23-24-25-26-27 13-14-15-WAIT-16-17-18-19-2021-22-23-24-25-26-27-28 14-15-WAIT-WAIT-16-17-18-1920-21-22-23-24-25-26-27-28-29
13-14-15-WAIT- 13-14-15-WAIT-1616 17-18-19-20 14-15-WAITWAIT-16-17 15-WAIT-WAITWAIT-16-17-18 14-15-WAIT-WAIT16-17-18-19-20-21
15
15-WAIT-WAIT15-WAIT-WAIT-WAIT-16-17-18-19WAIT-16-17-18-19- 20-21-22-23-24-25-26-27-28-2920-21-22 30
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Figure 6. X-Latency and Data Output Configuration Example
X-latency 1st cycle K 2nd cycle 3rd cycle 4th cycle
E
L
A22-A0 tDELAY
VALID ADDRESS tAVK_CPU tACC tQVK_CPU tKQV tK tQVK_CPU
DQ15-DQ0 VALID DATA VALID DATA
Note. Settings shown: X-latency = 4, Data Output held for one clock cycle
AI06182
Figure 7. Wait Configuration Example
E
K
L
A22-A0
VALID ADDRESS
DQ15-DQ0
VALID DATA VALID DATA
NOT VALID
VALID DATA
WAIT CR8 = '0' CR10 = '0' WAIT CR8 = '1' CR10 = '0' WAIT CR8 = '0' CR10 = '1' WAIT CR8 = '1' CR10 = '1'
AI06972
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READ MODES
Read operations can be performed in two different ways depending on the settings in the Configuration Register. If the clock signal is `don't care' for the data output, the read operation is asynchronous; if the data output is synchronized with clock, the read operation is synchronous. The read mode and format of the data output are determined by the Configuration Register. (See Configuration Register section for details). All banks support both asynchronous and synchronous read operations. Asynchronous Read Mode In Asynchronous Read operations the clock signal is `don't care'. The device outputs the data corresponding to the address latched, that is the memory array, Status Register, Common Flash Interface or Electronic Signature depending on the command issued. CR15 in the Configuration Register must be set to `1' for asynchronous operations. Asynchronous Read operations can be performed in two different ways, Asynchronous Random Access Read and Asynchronous Page Read. Only Asynchronous Page Read takes full advantage of the internal page storage so different timings are applied. In Asynchronous Read mode a Page of data is internally read and stored in a Page Buffer. The Page has a size of 4 Words and is addressed by address inputs A0 and A1. The first read operation within the Page has a longer access time (tAVQV, Random access time), subsequent reads within the same Page have much shorter access times (tAVQV1, Page access time). If the Page changes then the normal, longer timings apply again. The device features an Automatic Standby mode. During Asynchronous Read operations, after a bus inactivity of 150ns, the device automatically switches to the Automatic Standby mode. In this condition the power consumption is reduced to the standby value and the outputs are still driven. In Asynchronous Read mode, the WAIT signal is always de-asserted. See Table 21., Asynchronous Read AC Characteristics, Figure 10., Asynchronous Random Access Read AC Waveforms, and Figure 11., Asynchronous Page Read AC Waveforms, for details. Synchronous Burst Read Mode In Synchronous Burst Read mode the data is output in bursts synchronized with the clock. It is possible to perform burst reads across bank boundaries. Synchronous Burst Read mode can only be used to read the memory array. For other read operations, such as Read Status Register, Read CFI and Read Electronic Signature, Single Synchronous Read or Asynchronous Random Access Read must be used. In Synchronous Burst Read mode the flow of the data output depends on parameters that are configured in the Configuration Register. A burst sequence starts at the first clock edge (rising or falling depending on Valid Clock Edge bit CR6 in the Configuration Register) after the falling edge of Latch Enable or Chip Enable, whichever occurs last. Addresses are internally incremented and data is output on each data cycle after a delay which depends on the X latency bits CR13-CR11 of the Configuration Register. The number of Words to be output during a Synchronous Burst Read operation can be configured as 4 Words, 8 Words, 16 Words or Continuous (Burst Length bits CR2-CR0). The data can be configured to remain valid for one or two clock cycles (Data Output Configuration bit CR9). The order of the data output can be modified through the Wrap Burst bit in the Configuration Register. The burst sequence is sequential and can be confined inside the 4, 8 or 16 Word boundary (Wrap) or overcome the boundary (No Wrap). The WAIT signal may be asserted to indicate to the system that an output delay will occur. This delay will depend on the starting address of the burst sequence and on the burst configuration. WAIT is asserted during the X latency, the Wait state and at the end of a 4, 8 and 16 Word burst. It is only de-asserted when output data are valid. In Continuous Burst Read mode a Wait state will occur when crossing the first 16 Word boundary. If the burst starting address is aligned to a 4 Word Page, the Wait state will not occur. The WAIT signal can be configured to be active Low or active High by setting CR10 in the Configuration Register. See Table 22., Synchronous Read AC Characteristics, and Figure 12., Synchronous Burst Read AC Waveforms, for details. Synchronous Burst Read Suspend. A Synchronous Burst Read operation can be suspended, freeing the data bus for other higher priority devices. It can be suspended during the initial access latency time (before data is output) in which case the initial latency time can be reduced to zero, or after the device has output data. When the Synchronous Burst Read operation is suspended, internal array sensing continues and any previously latched internal data is retained. A burst se-
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quence can be suspended and resumed as often as required as long as the operating conditions of the device are met. A Synchronous Burst Read operation is suspended when Chip Enable, E, is Low and the current address has been latched (on a Latch Enable rising edge or on a valid clock edge). The Clock signal is then halted at VIH or at VIL, and Output Enable, G, goes High. When Output Enable, G, becomes Low again and the Clock signal restarts, the Synchronous Burst Read operation is resumed exactly where it stopped. WAIT will revert to high-impedance when Output Enable, G, or Chip Enable, E, goes High. See Table 22., Synchronous Read AC Characteristics, and Figure 14., Synchronous Burst Read Suspend AC Waveforms, for details. Single Synchronous Read Mode Single Synchronous Read operations are similar to Synchronous Burst Read operations except that the memory outputs the same data to the end of the operation. Synchronous Single Reads are used to read the Electronic Signature, Status Register, CFI, Block Protection Status, Configuration Register Status or Protection Register. When the addressed bank is in Read CFI, Read Status Register or Read Electronic Signature mode, the WAIT signal is asserted during the X latency, the Wait state and at the end of a 4, 8 and 16 Word burst. It is only deasserted when output data are valid. See Table 22., Synchronous Read AC Characteristics, and Figure 12., Synchronous Burst Read AC Waveforms, for details.
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M30L0R7000T0, M30L0R7000B0
DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTURE
The Multiple Bank Architecture of the M30L0R7000T0/B0 gives greater flexibility for software developers to split the code and data spaces within the memory array. The Dual Operations feature simplifies the software management of the device by allowing code to be executed from one bank while another bank is being programmed or erased. The Dual Operations feature means that while programming or erasing in one bank, read operations are possible in another bank with zero latency (only one bank at a time is allowed to be in program or erase mode). If a read operation is required in a bank, which is programming or erasing, the program or erase operation can be suspended. Table 12. Dual Operations Allowed In Other Banks
Commands allowed in another bank Status of bank Read Array Yes Yes Yes Yes Yes Read Status Register Yes Yes Yes Yes Yes Read CFI Query Yes Yes Yes Yes Yes Read Electronic Signature Yes Yes Yes Yes Yes Program, Buffer Program Yes - - - Yes Block Erase Yes - - - - Program/ Program/ Erase Erase Suspend Resume Yes Yes Yes - - Yes - - Yes Yes
Also if the suspended operation was erase then a program command can be issued to another block, so the device can have one block in Erase Suspend mode, one programming and other banks in read mode. Bus Read operations are allowed in another bank between setup and confirm cycles of program or erase operations. By using a combination of these features, read operations are possible at any moment in the M30L0R7000T0/B0 device. Tables 12 and 13 show the dual operations possible in other banks and in the same bank.
Idle Programming Erasing Program Suspended Erase Suspended
Table 13. Dual Operations Allowed In Same Bank
Commands allowed in same bank Status of bank Read Array Yes -(2) -(2) Yes(1) Yes(1) Read Read Read Status Electronic CFI Query Register Signature Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Program, Buffer Program Yes - - - Yes(1) Block Erase Yes - - - - Program/ Program/ Erase Erase Suspend Resume Yes Yes Yes - - Yes - - Yes Yes
Idle Programming Erasing Program Suspended Erase Suspended
Note: 1. Not allowed in the Block or Word that is being erased or programmed. 2. The Read Array command is accepted but the data output is not guaranteed until the Program or Erase has completed.
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BLOCK LOCKING
The M30L0R7000T0/B0 features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. This locking scheme has three levels of protection. Lock/Unlock - this first level allows software only control of block locking.
Lock-Down - this second level requires hardware interaction before locking can be changed. VPP VPPLK - the third level offers a complete hardware protection against program and erase on all blocks.
The protection status of each block can be set to Locked, Unlocked, and Locked-Down. Table 14., defines all of the possible protection states (WP, DQ1, DQ0), and APPENDIX C., Figure 27., shows a flowchart for the locking operations. Reading a Block's Lock Status The lock status of every block can be read in the Read Electronic Signature mode of the device. To enter this mode issue the Read Electronic Signature command. Subsequent reads at the address specified in Table 7., will output the protection status of that block. The lock status is represented by DQ0 and DQ1. DQ0 indicates the Block Lock/Unlock status and is set by the Lock command and cleared by the Unlock command. DQ0 is automatically set when entering Lock-Down. DQ1 indicates the Lock-Down status and is set by the Lock-Down command. DQ1 cannot be cleared by software, only by a hardware reset or power-down. The following sections explain the operation of the locking system. Locked State The default status of all blocks on power-up or after a hardware reset is Locked (states (0,0,1) or (1,0,1)). Locked blocks are fully protected from program or erase operations. Any program or erase operations attempted on a locked block will return an error in the Status Register. The Status of a Locked block can be changed to Unlocked or Locked-Down using the appropriate software commands. An Unlocked block can be Locked by issuing the Lock command. Unlocked State Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. All unlocked blocks return to the Locked state after a hardware reset or when the device is powered-down. The status of an unlocked block can be changed to
Locked or Locked-Down using the appropriate software commands. A locked block can be unlocked by issuing the Unlock command. Lock-Down State Blocks that are Locked-Down (state (0,1,x))are protected from program and erase operations (as for Locked blocks) but their protection status cannot be changed using software commands alone. A Locked or Unlocked block can be Locked-Down by issuing the Lock-Down command. LockedDown blocks revert to the Locked state when the device is reset or powered-down. The Lock-Down function is dependent on the Write Protect, WP, input pin. When WP=0 (VIL), the blocks in the Lock-Down state (0,1,x) are protected from program, erase and protection status changes. When WP=1 (VIH) the Lock-Down function is disabled (1,1,x) and Locked-Down blocks can be individually unlocked to the (1,1,0) state by issuing the software command, where they can be erased and programmed. When the Lock-Down function is disabled (WP=1) blocks can be locked (1,1,1) and unlocked (1,1,0) as desired. When WP=0 blocks that were previously Locked-Down return to the Lock-Down state (0,1,x) regardless of any changes that were made while WP=1. Device reset or power-down resets all blocks, including those in Lock-Down, to the Locked state. Locking Operations During Erase Suspend Changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock or lock-down a block. This is useful in the case when another block needs to be updated while an erase operation is in progress. To change block locking during an erase operation, first write the Erase Suspend command, then check the Status Register until it indicates that the erase operation has been suspended. Next write the desired Lock command sequence to a block and the lock status will be changed. After completing any desired lock, read, or program operations, resume the erase operation with the Erase Resume command. If a block is locked or locked-down during an erase suspend of the same block, the locking status bits will be changed immediately, but when the erase is resumed, the erase operation will complete. Locking operations cannot be performed during a program suspend.
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Table 14. Lock Status
Current Protection Status(1) (WP, DQ1, DQ0) Current State 1,0,0 1,0,1(2) 1,1,0 1,1,1 0,0,0 0,0,1(2) 0,1,1 Program/Erase Allowed yes no yes no yes no no After Block Lock Command 1,0,1 1,0,1 1,1,1 1,1,1 0,0,1 0,0,1 0,1,1 Next Protection Status(1) (WP, DQ1, DQ0) After Block Unlock Command 1,0,0 1,0,0 1,1,0 1,1,0 0,0,0 0,0,0 0,1,1 After Block Lock-Down Command 1,1,1 1,1,1 1,1,1 1,1,1 0,1,1 0,1,1 0,1,1 After WP transition 0,0,0 0,0,1 0,1,1 0,1,1 1,0,0 1,0,1 1,1,1 or 1,1,0 (3)
Note: 1. The lock status is defined by the write protect pin and by DQ1 (`1' for a locked-down block) and DQ0 (`1' for a locked block) as read in the Read Electronic Signature command with A1 = VIH and A0 = VIL. 2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status. 3. A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.
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M30L0R7000T0, M30L0R7000B0
PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES
The Program and Erase times and the number of Program/ Erase cycles per block are shown in Table 15. In the M30L0R7000T0/B0 the maximum number of Program/ Erase cycles depends on the voltage supply used.
Table 15. Program, Erase Times and Endurance Cycles
Parameter Condition Min Typ 0.65 0.8 1.4 1.8 10 10 10 10 320 640 5 5 100,000 100,000 0.7 1.2 10 10 3.5 320 100 640 200 5 1.6 1000 2500 2.5 4 100 100 10 25 100 3 Typical after 100k W/E Cycles 1 Max 2.5 2.5 4 4 100 Unit s s s s s s s s s ms s s cycles cycles s s s s s s s ms ms s s cycles cycles
Erase
Parameter Block Preprogrammed (16 KWords) Not Preprogrammed Main Block (64 KWords) Single Cell Preprogrammed Not Preprogrammed Word Program Buffer Program Word Program Buffer Program
VPP = VDD
Program(3)
Single Word
Buffer (32 Words) (Buffer Program) Main Block (64 KWords) Suspend Latency Program Erase
Main Blocks Program/Erase Cycles (per Block) Parameter Blocks Erase Parameter Block (16 KWords) Main Block (64 KWords) Single Cell Single Word Word Program Word Program Buffered Enhanced Factory Program(4) Word Program VPP = VPPH Program(3) Buffer (32 Words) Buffered Enhanced Factory Program(4) Word Program Main Block (64 KWords) Buffered Enhanced Factory Program(4) Word Program Bank (8 Mbits) Main Blocks Program/Erase Cycles (per Block) Parameter Blocks
Note: 1. 2. 3. 4.
Buffered Enhanced Factory Program(4)
TA = -40 to 85C; VDD = 1.7V to 2.0V; VDDQ = 1.7V to 2.0V. Values are liable to change with the external system-level overhead (command sequence and Status Register polling execution). Excludes the time needed to execute the command sequence. Average on entire device.
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MAXIMUM RATING
Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not imTable 16. Absolute Maximum Ratings
Value Symbol TA TBIAS TSTG TLEAD VIO VDD VDDQ VPP IO tVPPH Parameter Min Ambient Operating Temperature Temperature Under Bias Storage Temperature Lead Temperature during Soldering Input or Output Voltage Supply Voltage Input/Output Supply Voltage Program Voltage Output Short Circuit Current Time for VPP at VPPH -0.5 -0.2 -0.2 -0.2 -25 -25 -65 Max 85 85 125
(1)
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Unit C C C C V V V V mA hours
3.8 2.5 2.5 14 100 100
Note: 1. Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK(R) 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.
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DC AND AC PARAMETERS
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 17., Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters.
Table 17. Operating and AC Measurement Conditions
M30L0R7000T0, M30L0R7000B0 Parameter Min VDD Supply Voltage VDDQ Supply Voltage VPP Supply Voltage (Factory environment) VPP Supply Voltage (Application environment) Ambient Operating Temperature Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 0 to VDDQ VDDQ/2 1.7 1.7 8.5 -0.4 -25 30 5 85 Max 2.0 2.0 12.6 VDDQ+0.4 85 V V V V C pF ns V V Units
Figure 8. AC Measurement I/O Waveform
Figure 9. AC Measurement Load Circuit
VDDQ
VDDQ VDDQ/2 0V VDDQ VDD 16.7k
AI06161
DEVICE UNDER TEST 0.1F 0.1F CL 16.7k
CL includes JIG capacitance
AI06162
Table 18. Capacitance
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min 6 8 Max 8 12 Unit pF pF
Note: Sampled only, not 100% tested.
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Table 19. DC Characteristics - Currents
Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current Supply Current Asynchronous Read (f=6MHz) Test Condition 0V VIN VDDQ 0V VOUT VDDQ E = VIL, G = VIH 4 Word Supply Current Synchronous Read (f=40MHz) IDD1 8 Word 16 Word Continuous 4 Word Supply Current Synchronous Read (f=54MHz) 8 Word 16 Word Continuous IDD2 IDD3 IDD4 Supply Current (Reset) Supply Current (Standby) Supply Current (Automatic Standby) Supply Current (Program) IDD5 (1) Supply Current (Erase) VPP = VDD Program/Erase in one Bank, Asynchronous Read in another Bank Program/Erase in one Bank, Synchronous Read in another Bank E = VDD 0.2V VPP = VPPH VPP = VDD VPP = VPPH VPP = VDD VPP VDD VPP VDD 10 20 20 35 mA mA VPP = VDD VPP = VPPH 10 8 20 15 mA mA RP = VSS 0.2V E = VDD 0.2V E = VIL, G = VIH VPP = VPPH 10 7 10 13 18 16 18 21 22 25 25 25 8 Min Typ Max 1 1 15 16 18 20 25 18 20 25 27 70 70 70 15 Unit A A mA mA mA mA mA mA mA mA mA A A A mA
Supply Current IDD6 (1,2) (Dual Operations)
32
47
mA
IDD7(1)
Supply Current Program/ Erase Suspended (Standby) VPP Supply Current (Program)
25 2 0.2 2 0.2 0.2 0.2
70 5 5 5 5 5 5
A mA A mA A A A
IPP1(1) VPP Supply Current (Erase) IPP2 IPP3(1) VPP Supply Current (Read) VPP Supply Current (Standby)
Note: 1. Sampled only, not 100% tested. 2. VDD Dual Operation current is the sum of read and program or erase currents.
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Table 20. DC Characteristics - Voltages
Symbol VIL VIH VOL VOH VPP1 VPPH VPPLK VLKO VRPH Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VPP Program Voltage-Logic VPP Program Voltage Factory Program or Erase Lockout VDD Lock Voltage RP pin Extended High Voltage 1 3.3 IOL = 100A IOH = -100A Program, Erase Program, Erase VDDQ -0.1 1.1 8.5 1.8 9.0 3.3 12.6 0.4 Test Condition Min -0.5 VDDQ -0.4 Typ Max 0.4 VDDQ + 0.4 0.1 Unit V V V V V V V V V
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tAVAV VALID VALID tLHAX tAVQV tAXQX tAVLH tLLLH tLLQV tELLH tELQV tELQX tEHQZ tEHQX tGLQV tGLQX VALID tGLTV tELTV tGHTZ tEHTZ tGHQX tGHQZ
AI08311
A0-A22
M30L0R7000T0, M30L0R7000B0
L
E
Figure 10. Asynchronous Random Access Read AC Waveforms
G
DQ0-DQ15
Hi-Z
WAIT
Hi-Z
Note. Write Enable, W, is High, WAIT is active Low.
M30L0R7000T0, M30L0R7000B0
Figure 11. Asynchronous Page Read AC Waveforms
A2-A22 tAVAV A0-A1 VALID ADDRESS tAVLH L tLLLH tLLQV tELLH E tELQV tELQX G tGLTV WAIT (1) Hi-Z tELTV tLHAX
VALID ADDRESS
VALID ADD. VALID ADD. VALID ADD.
tGLQV tGLQX DQ0-DQ15 VALID DATA Outputs Valid Address Latch Enabled tAVQV1 VALID DATA VALID DATA VALID DATA
Valid Data
Standby
Note 1. WAIT is active Low.
AI08334
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Table 21. Asynchronous Read AC Characteristics
Symbol tAVAV tAVQV tAVQV1 tAXQX (1) tELTV tELQV (2) Read Timings tELQX (1) tEHTZ tEHQX
(1)
Alt tRC tACC tPAGE tOH
Parameter Address Valid to Next Address Valid Address Valid to Output Valid (Random) Address Valid to Output Valid (Page) Address Transition to Output Transition Chip Enable Low to Wait Valid Min Max Max Min Max Max Min Max Min Max Max Min Max Min Max Max Min Min Min Min Max
M30L0R7000T0/B0 85 85 85 25 0 14 85 0 17 0 17 20 0 14 0 17 17 7 10 7 7 85
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tCE tLZ
Chip Enable Low to Output Valid Chip Enable Low to Output Transition Chip Enable High to Wait Hi-Z
tOH tHZ tOE tOLZ
Chip Enable High to Output Transition Chip Enable High to Output Hi-Z Output Enable Low to Output Valid Output Enable Low to Output Transition Output Enable Low to Wait Valid
tEHQZ (1) tGLQV (2) tGLQX (1) tGLTV tGHQX (1) tGHQZ (1) tGHTZ tAVLH
tOH tDF
Output Enable High to Output Transition Output Enable High to Output Hi-Z Output Enable High to Wait Hi-Z
tAVADVH tELADVH tADVHAX
Address Valid to Latch Enable High Chip Enable Low to Latch Enable High Latch Enable High to Address Transition
Latch Timings
tELLH tLHAX tLLLH tLLQV
tADVLADVH Latch Enable Pulse Width tADVLQV Latch Enable Low to Output Valid (Random)
Note: 1. Sampled only, not 100% tested. 2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV.
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DQ0-DQ15 VALID tKHQV tKHQX VALID VALID NOT VALID VALID
Hi-Z
A0-A22
VALID ADDRESS
tAVLH tLLLH
L tEHQX tEHQZ Note 1 tEHEL
tLLKH
tAVKH
K(4)
tELKH
tKHAX
Figure 12. Synchronous Burst Read AC Waveforms
E tGHQX tGLQX tGHQZ
G tGLTV tKHTV Note 2 tKHTX Note 2 Note 2 Valid Valid Data Flow Boundary Crossing Data tEHTZ
tELTV
Hi-Z
WAIT X Latency
Address Latch
Standby
M30L0R7000T0, M30L0R7000B0
Note 1. The number of clock cycles to be inserted depends on the X latency set in the Burst Configuration Register. 2. The WAIT signal can be configured to be active during wait state or one cycle before. WAIT signal is active Low. 3. Address latched and data output on the rising clock edge. 4. Either the rising or the falling edge of the clock signal, K, can be configured as the active edge. Here, the active edge of K is the rising one.
AI10197
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M30L0R7000T0, M30L0R7000B0
Figure 13. Single Synchronous Read AC Waveforms
A0-A22 VALID ADDRESS tAVKH L tLLKH K(2) tELKH tELQV E tGLQV tGLQX G tELQX DQ0-DQ15 Hi-Z VALID tKHTV tGLTV WAIT(1,2) Hi-Z tGHTZ tKHQV
Note 1. The WAIT signal is configured to be active during wait state. WAIT signal is active Low. 2. Address latched and data output on the rising clock edge. Either the rising or the falling edge of the clock signal, K, can be configured as the active edge. Here, the active edge is the rising one.
AI08312
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Hi-Z
VALID VALID NOT VALID NOT VALID
DQ0-DQ15
A0-A22
VALID ADDRESS
tAVLH tLLLH
L tEHQX tKHQV Note 1 Note 3 tEHEL tEHQZ
tLLKH
tAVKH
K(4)
tELKH
tKHAX
E tGLQX tGLQV tGHQZ tGLQV tGHQX tGHQZ
Figure 14. Synchronous Burst Read Suspend AC Waveforms
G tGLTV tELTV tGHTZ tGLTV tEHTZ
Hi-Z
WAIT(2)
M30L0R7000T0, M30L0R7000B0
Note 1. The number of clock cycles to be inserted depends on the X latency set in the Configuration Register. 2. The WAIT signal is configured to be active during wait state. WAIT signal is active Low. 3. The CLOCK signal can be held high or low 4. Address latched and data output on the rising clock edge. Either the rising or the falling edge of the clock signal, K, can be configured as the active edge. Here, the active edge is the rising one.
AI08308
45/83
M30L0R7000T0, M30L0R7000B0
Figure 15. Clock input AC Waveform
tKHKL
tKHKH
tf
tr
tKLKH
AI06981
Table 22. Synchronous Read AC Characteristics
M30L0R7000T0/B0 Symbol tAVKH tELKH Synchronous Read Timings tELTV tEHEL tEHTZ tKHAX tKHQV tKHTV tKHQX tKHTX tLLKH tCLKHAX tCLKHQV tCLKHQX tADVLCLKH Alt tAVCLKH tELCLKH Parameter 85 Address Valid to Clock High Chip Enable Low to Clock High Chip Enable Low to Wait Valid Chip Enable Pulse Width (subsequent synchronous reads) Chip Enable High to Wait Hi-Z Clock High to Address Transition Clock High to Output Valid Clock High to WAIT Valid Clock High to Output Transition Clock High to WAIT Transition Latch Enable Low to Clock High Clock Period (f=40MHz) Clock Specifications tKHKH tCLK Clock Period (f=47MHz) Clock Period (f=54MHz) tKHKL tKLKH tf tr Clock High to Clock Low Clock Low to Clock High Clock Fall or Rise Time Min Min Max Min Max Min Max 7 7 14 14 17 7 14 ns ns ns ns ns ns ns Unit
Min Min Min Min Min Min
3 7
ns ns ns
18.5 3.5
ns ns
Max
3
ns
Note: 1. Sampled only, not 100% tested. 2. For other timings please refer to Table 21., Asynchronous Read AC Characteristics.
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PROGRAM OR ERASE tAVAV BANK ADDRESS VALID ADDRESS tAVWH tWHAV tWHAX VALID ADDRESS tLHAX tLLLH
A0-A22
tAVLH
L tWHLL
tELLH
E tWHEH
tELWL
G tWHWL tWHGL
tGHWL
W tWLWH tWHEL tWHDX COMMAND CMD or DATA tWHWPL tWPHWH tQVWPL tWHQV STATUS REGISTER tELQV
Figure 16. Write AC Waveforms, Write Enable Controlled
tDVWH
DQ0-DQ15
WP tWHVPL tVPHWH tQVVPL
VPP tELKV
K CONFIRM COMMAND OR DATA INPUT STATUS REGISTER READ 1st POLLING
AI08016
M30L0R7000T0, M30L0R7000B0
SET-UP COMMAND
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M30L0R7000T0, M30L0R7000B0
Table 23. Write AC Characteristics, Write Enable Controlled
M30L0R7000T0/B0 Symbol tAVAV tAVLH tAVWH(3) tDVWH tELLH tELWL tELQV Write Enable Controlled Timings tELKV tGHWL tLHAX tLLLH tWHAV(3) tWHAX(3) tWHDX tWHEH tWHEL(2) tWHGL tWHLL tWHWL tWHQV tWLWH tQVVPL Protection Timings tQVWPL tVPHWH tWHVPL tWHWPL tWPHWH tWP tAH tDH tCH tCS tDS Alt tWC Parameter 85 Address Valid to Next Address Valid Address Valid to Latch Enable High Address Valid to Write Enable High Data Valid to Write Enable High Chip Enable Low to Latch Enable High Chip Enable Low to Write Enable Low Chip Enable Low to Output Valid Chip Enable Low to Clock Valid Output Enable High to Write Enable Low Latch Enable High to Address Transition Latch Enable Pulse Width Write Enable High to Address Valid Write Enable High to Address Transition Write Enable High to Input Transition Write Enable High to Chip Enable High Write Enable High to Chip Enable Low Write Enable High to Output Enable Low Write Enable High to Latch Enable Low tWPH Write Enable High to Write Enable Low Write Enable High to Output Valid Write Enable Low to Write Enable High Output (Status Register) Valid to VPP Low Output (Status Register) Valid to Write Protect Low tVPS VPP High to Write Enable High Write Enable High to VPP Low Write Enable High to Write Protect Low Write Protect High to Write Enable High Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min 85 7 50 50 10 0 85 9 17 9 9 0 0 0 0 25 0 0 25 110 50 0 0 200 200 200 200 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. Sampled only, not 100% tested. 2. tWHEL has the values shown when reading in the targeted bank. System designers should take this into account and may insert a software No-Op instruction to delay the first read in the same bank after issuing a command. If it is a Read Array operation in a different bank tWHEL is 0ns. 3. Meaningful only if L is always kept low.
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PROGRAM OR ERASE tAVAV BANK ADDRESS VALID ADDRESS tAVEH tEHAX VALID ADDRESS tLHAX tLLLH
A0-A22
tAVLH
L tELLH tEHWH
W
tWLEL
G tEHEL tEHGL
tGHEL
E tELEH tEHDX COMMAND CMD or DATA tEHWPL tWPHEH tQVWPL tWHEL tWHQV tELQV
Figure 17. Write AC Waveforms, Chip Enable Controlled
tDVEH
DQ0-DQ15
STATUS REGISTER
WP tEHVPL tVPHEH tQVVPL
VPP tELKV
K CONFIRM COMMAND OR DATA INPUT STATUS REGISTER READ 1st POLLING
SET-UP COMMAND
M30L0R7000T0, M30L0R7000B0
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AI08017
M30L0R7000T0, M30L0R7000B0
Table 24. Write AC Characteristics, Chip Enable Controlled
M30L0R7000T0/B0 Symbol tAVAV tAVEH tAVLH tDVEH tEHAX tEHDX Chip Enable Controlled Timings tEHEL tEHGL tEHWH tELKV tELEH tELLH tELQV tGHEL tLHAX tLLLH tWHEL(2) tWHQV tWLEL tEHVPL Protection Timings tEHWPL tQVVPL tQVWPL tVPHEH tWPHEH tVPS tCS tCP tCH tDS tAH tDH tCPH Alt tWC Parameter 85 Address Valid to Next Address Valid Address Valid to Chip Enable High Address Valid to Latch Enable High Data Valid to Write Enable High Chip Enable High to Address Transition Chip Enable High to Input Transition Chip Enable High to Chip Enable Low Chip Enable High to Output Enable Low Chip Enable High to Write Enable High Chip Enable Low to Clock Valid Chip Enable Low to Chip Enable High Chip Enable Low to Latch Enable High Chip Enable Low to Output Valid Output Enable High to Chip Enable Low Latch Enable High to Address Transition Latch Enable Pulse Width Write Enable High to Chip Enable Low Write Enable High to Output Valid Write Enable Low to Chip Enable Low Chip Enable High to VPP Low Chip Enable High to Write Protect Low Output (Status Register) Valid to VPP Low Output (Status Register) Valid to Write Protect Low VPP High to Chip Enable High Write Protect High to Chip Enable High Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min 85 50 7 50 0 0 25 0 0 9 50 10 85 17 9 9 25 110 0 200 200 0 0 200 200 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. Sampled only, not 100% tested. 2. tWHEL has the values shown when reading in the targeted bank. System designers should take this into account and may insert a software No-Op instruction to delay the first read in the same bank after issuing a command. If it is a Read Array operation in a different bank tWHEL is 0ns.
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M30L0R7000T0, M30L0R7000B0
Figure 18. Reset and Power-up AC Waveforms
W, E, G, L
tPHWL tPHEL tPHGL tPHLL
tPLWL tPLEL tPLGL tPLLL
RP tVDHPH VDD, VDDQ Power-Up Reset
AI06976
tPLPH
Table 25. Reset and Power-up AC Characteristics
Symbol tPLWL tPLEL tPLGL tPLLL tPHWL tPHEL tPHGL tPHLL tPLPH (1,2) tVDHPH (3) Parameter Reset Low to Write Enable Low, Chip Enable Low, Output Enable Low, Latch Enable Low Reset High to Write Enable Low Chip Enable Low Output Enable Low Latch Enable Low RP Pulse Width Supply Voltages High to Reset High Test Condition During Program During Erase Other Conditions Min Min Min 85 10 25 80 Unit s s ns
Min
30
ns
Min Min
50 50
ns s
Note: 1. The device Reset is possible but not guaranteed if tPLPH < 50ns. 2. Sampled only, not 100% tested. 3. It is important to assert RP in order to allow proper CPU initialization during Power-Up or Reset.
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M30L0R7000T0, M30L0R7000B0
PACKAGE MECHANICAL
Figure 19. TFBGA88 8x10mm - 8x10 ball array, 0.8mm pitch, Bottom View Package Outline
D D1
e SE E E2 E1 b BALL "A1"
ddd FE FE1 A A1 FD SD A2
BGA-Z42
Note: Drawing is not to scale.
Table 26. TFBGA88 8x10mm - 8x10 ball array, 0.8mm pitch, Package Mechanical Data
millimeters Symbol Typ A A1 A2 b D D1 ddd E E1 E2 e FD FE FE1 SD SE 10.000 7.200 8.800 0.800 1.200 1.400 0.600 0.400 0.400 - - 9.900 0.850 0.350 8.000 5.600 0.100 10.100 0.3937 0.2835 0.3465 0.0315 0.0472 0.0551 0.0236 0.0157 0.0157 - - 0.3898 0.300 7.900 0.400 8.100 0.200 0.0335 0.0138 0.3150 0.2205 0.0039 0.3976 0.0118 0.3110 0.0157 0.3189 Min Max 1.200 0.0079 Typ Min Max 0.0472 inches
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M30L0R7000T0, M30L0R7000B0
Figure 20. TFBGA88 Daisy Chain - Package Connections (Top view through package)
1 2 3 4 5 6 7 8
A
B
C
D
E
F
G
H
J
K
L
M
AI08304
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M30L0R7000T0, M30L0R7000B0
Figure 21. TFBGA88 Daisy Chain - PCB Connection Proposal (Top view through package)
1 START POINT A END POINT 2 3 4 5 6 7 8
B
C
D
E
F
G
H
J
K
L
M
AI08305
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M30L0R7000T0, M30L0R7000B0
PART NUMBERING
Table 27. Ordering Information Scheme
Example: Device Type M30 = Multiple Flash Memory Product Flash Device Identifier 1 L = Multilevel, Multiple Bank, Burst Mode Flash Device Identifier 2 0 = no other architecture Operating Voltage R = VDD = VDDQ = 1.8V typical Flash 1 Density 7 = 128 Mbit Flash 2 Density 0 = No Die Flash 3 Density 0 = No Die Flash 4 Density 0 = No Die Parameter Block Location T = Top Boot Block B = Bottom Boot Block Product Version 0 = Flash 0.13m, 85ns Package ZAQ = TFBGA88 8 x 10mm, 0.80mm pitch, quadruple stacked footprint Option Blank = Standard Packing T = Tape & Reel packing E = Lead-Free and RoHS Package, Standard Packing F = Lead-Free and RoHS Package, Tape & Reel Packing M30 L 0 R7000T 0 ZAQ T
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M30L0R7000T0, M30L0R7000B0
Table 28. Daisy Chain Ordering Scheme
Example: Device Type M30L0R7000T0 Daisy Chain ZAQ = LFBGA88 8 x 10mm, 0.80mm pitch, quadruple stacked footprint Option Blank = Standard Packing T = Tape & Reel packing E = Lead-Free and RoHS Package, Standard Packing F = Lead-Free and RoHS Package, Tape & Reel Packing M30L0R7000 -ZAQ T
Devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
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M30L0R7000T0, M30L0R7000B0
APPENDIX A. BLOCK ADDRESS TABLES
Table 29. Top Boot Block Addresses, M30L0R7000T0
Bank # 0 1 2 Parameter Bank 3 4 5 6 7 8 9 10 11 12 13 Bank 1 14 15 16 17 18 19 20 21 Bank 2 22 23 24 25 26 27 28 29 Bank 3 30 31 32 33 34 Bank 4 Size (KWord) 16 16 16 16 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 Address Range 7FC000-7FFFFF 7F8000-7FBFFF 7F4000-7F7FFF 7F0000-7F3FFF 7E0000-7EFFFF 7D0000-7DFFFF 7C0000-7CFFFF Bank 5 7B0000-7BFFFF 7A0000-7AFFFF 790000-79FFFF 780000-78FFFF 770000-77FFFF 760000-76FFFF 750000-75FFFF 740000-74FFFF Bank 6 730000-73FFFF 720000-72FFFF 710000-71FFFF 700000-70FFFF 6F0000-6FFFFF 6E0000-6EFFFF 6D0000-6DFFFF 6C0000-6CFFFF Bank 7 6B0000-6BFFFF 6A0000-6AFFFF 690000-69FFFF 680000-68FFFF 670000-67FFFF 660000-66FFFF 650000-65FFFF 640000-64FFFF Bank 8 630000-63FFFF 620000-62FFFF 610000-61FFFF 600000-60FFFF 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 5F0000-5FFFFF 5E0000-5EFFFF 5D0000-5DFFFF 5C0000-5CFFFF 5B0000-5BFFFF 5A0000-5AFFFF 590000-59FFFF 580000-58FFFF 570000-57FFFF 560000-56FFFF 550000-55FFFF 540000-54FFFF 530000-53FFFF 520000-52FFFF 510000-51FFFF 500000-50FFFF 4F0000-4FFFFF 4E0000-4EFFFF 4D0000-4DFFFF 4C0000-4CFFFF 4B0000-4BFFFF 4A0000-4AFFFF 490000-49FFFF 480000-48FFFF 470000-47FFFF 460000-46FFFF 450000-45FFFF 440000-44FFFF 430000-43FFFF 420000-42FFFF 410000-41FFFF 400000-40FFFF 3F0000-3FFFFF 3E0000-3EFFFF 3D0000-3DFFFF 3C0000-3CFFFF 3B0000-3BFFFF 3A0000-3AFFFF 390000-39FFFF 380000-38FFFF
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M30L0R7000T0, M30L0R7000B0
75 76 77 Bank 9 78 79 80 81 82 83 84 85 Bank 10 86 87 88 89 90 91 92 93 Bank 11 94 95 96 97 98 99 100 101 Bank 12 102 103 104 105 106 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 370000-37FFFF 360000-36FFFF 350000-35FFFF 340000-34FFFF 330000-33FFFF 320000-32FFFF 310000-31FFFF 300000-30FFFF 2F0000-2FFFFF 2E0000-2EFFFF 2D0000-2DFFFF 2C0000-2CFFFF 2B0000-2BFFFF 2A0000-2AFFFF 290000-29FFFF 280000-28FFFF 270000-27FFFF 260000-26FFFF 250000-25FFFF 240000-24FFFF 230000-23FFFF 220000-22FFFF 210000-21FFFF 200000-20FFFF 1F0000-1FFFFF 1E0000-1EFFFF 1D0000-1DFFFF 1C0000-1CFFFF 1B0000-1BFFFF 1A0000-1AFFFF 190000-19FFFF 180000-18FFFF Bank 15 Bank 14 Bank 13 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 170000-17FFFF 160000-16FFFF 150000-15FFFF 140000-14FFFF 130000-13FFFF 120000-12FFFF 110000-11FFFF 100000-10FFFF 0F0000-0FFFFF 0E0000-0EFFFF 0D0000-0DFFFF 0C0000-0CFFFF 0B0000-0BFFFF 0A0000-0AFFFF 090000-09FFFF 080000-08FFFF 070000-07FFFF 060000-06FFFF 050000-05FFFF 040000-04FFFF 030000-03FFFF 020000-02FFFF 010000-01FFFF 000000-00FFFF
Note: There are two Bank Regions: Bank Region 1 contains all the banks that are made up of main blocks only; Bank Region 2 contains the banks that are made up of the parameter and main blocks (Parameter Bank).
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M30L0R7000T0, M30L0R7000B0
Table 30. Bottom Boot Block Addresses, M30L0R7000B0
Bank # 130 129 128 Bank 15 127 126 125 124 123 122 121 120 Bank 14 119 118 117 116 115 114 113 112 Bank 13 111 110 109 108 107 106 105 104 Bank 12 103 102 101 100 99 98 97 96 Bank 11 95 94 93 92 91 Bank 10 Size (KWord) 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 Address Range 7F0000-7FFFFF 7E0000-7EFFFF 7D0000-7DFFFF 7C0000-7CFFFF 7B0000-7BFFFF 7A0000-7AFFFF 790000-79FFFF Bank 9 780000-78FFFF 770000-77FFFF 760000-76FFFF 750000-75FFFF 740000-74FFFF 730000-73FFFF 720000-72FFFF 710000-71FFFF Bank 8 700000-70FFFF 6F0000-6FFFFF 6E0000-6EFFFF 6D0000-6DFFFF 6C0000-6CFFFF 6B0000-6BFFFF 6A0000-6AFFFF 690000-69FFFF Bank 7 680000-68FFFF 670000-67FFFF 660000-66FFFF 650000-65FFFF 640000-64FFFF 630000-63FFFF 620000-62FFFF 610000-61FFFF Bank 6 600000-60FFFF 5F0000-5FFFFF 5E0000-5EFFFF 5D0000-5DFFFF 5C0000-5CFFFF 5B0000-5BFFFF 5A0000-5AFFFF 590000-59FFFF 580000-58FFFF 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 570000-57FFFF 560000-56FFFF 550000-55FFFF 540000-54FFFF 530000-53FFFF 520000-52FFFF 510000-51FFFF 500000-50FFFF 4F0000-4FFFFF 4E0000-4EFFFF 4D0000-4DFFFF 4C0000-4CFFFF 4B0000-4BFFFF 4A0000-4AFFFF 490000-49FFFF 480000-48FFFF 470000-47FFFF 460000-46FFFF 450000-45FFFF 440000-44FFFF 430000-43FFFF 420000-42FFFF 410000-41FFFF 400000-40FFFF 3F0000-3FFFFF 3E0000-3EFFFF 3D0000-3DFFFF 3C0000-3CFFFF 3B0000-3BFFFF 3A0000-3AFFFF 390000-39FFFF 380000-38FFFF 370000-37FFFF 360000-36FFFF 350000-35FFFF 340000-34FFFF 330000-33FFFF 320000-32FFFF 310000-31FFFF 300000-30FFFF
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M30L0R7000T0, M30L0R7000B0
50 49 48 Bank 5 47 46 45 44 43 42 41 40 Bank 4 39 38 37 36 35 34 33 32 Bank 3 31 30 29 28 27 26 25 24 Bank 2 23 22 21 20 19 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 2F0000-2FFFFF 2E0000-2EFFFF 2D0000-2DFFFF 2C0000-2CFFFF 2B0000-2BFFFF 2A0000-2AFFFF 290000-29FFFF 280000-28FFFF 270000-27FFFF 260000-26FFFF 250000-25FFFF 240000-24FFFF 230000-23FFFF 220000-22FFFF 210000-21FFFF 200000-20FFFF 1F0000-1FFFFF 1E0000-1EFFFF 1D0000-1DFFFF 1C0000-1CFFFF 1B0000-1BFFFF 1A0000-1AFFFF 190000-19FFFF 180000-18FFFF 170000-17FFFF 160000-16FFFF 150000-15FFFF 140000-14FFFF 130000-13FFFF 120000-12FFFF 110000-11FFFF 1F0000-1FFFFF Parameter Bank Bank 1 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 16 16 16 16 0F0000-0FFFFF 0E0000-0EFFFF 0D0000-0DFFFF 0C0000-0CFFFF 0B0000-0BFFFF 0A0000-0AFFFF 090000-09FFFF 080000-08FFFF 070000-07FFFF 060000-06FFFF 050000-05FFFF 040000-04FFFF 030000-03FFFF 020000-02FFFF 010000-01FFFF 00C000-00FFFF 008000-00BFFF 004000-007FFF 000000-003FFF
Note: There are two Bank Regions: Bank Region 2 contains all the banks that are made up of main blocks only; Bank Region 1 contains the banks that are made up of the parameter and main blocks (Parameter Bank).
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M30L0R7000T0, M30L0R7000B0
APPENDIX B. COMMON FLASH INTERFACE
The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary. When the Read CFI Query Command is issued the device enters CFI Query mode and the data structure is read from the memory. Tables 31, 32, 33, 34, 35, 36, 37, 38, 39 and 40 show the adTable 31. Query Structure Overview
Offset 000h 010h 01Bh 027h P A 080h Reserved CFI Query Identification String System Interface Information Device Geometry Definition Primary Algorithm-specific Extended Query table Alternate Algorithm-specific Extended Query table Security Code Area Sub-section Name Description Reserved for algorithm-specific information Command set ID and algorithm data offset Device timing & voltage information Flash device layout Additional information specific to the Primary Algorithm (optional) Additional information specific to the Alternate Algorithm (optional) Lock Protection Register Unique device Number and User Programmable OTP
dresses used to retrieve the data. The Query data is always presented on the lowest order data outputs (DQ0-DQ7), the other outputs (DQ8-DQ15) are set to 0. The CFI data structure also contains a security area where a 64 bit unique security number is written (see Figure 5., Protection Register Memory Map). This area can be accessed only in Read mode by the final user. It is impossible to change the security number after it has been written by ST. Issue a Read Array command to return to Read mode.
Note: The Flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main sub-sections detailed in Tables 32, 33, 34, and 35. Query data is always presented on the lowest order data outputs.
Table 32. CFI Query Identification String
Offset 000h 001h 002h 003h 004h-00Fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah Sub-section Name 0020h 88C4h 88C5h Reserved Reserved Reserved 0051h 0052h 0059h 0003h 0000h offset = P = 000Ah 0001h 0000h 0000h value = A = 0000h 0000h Primary Algorithm Command Set and Control Interface ID code 16 bit ID code defining a specific algorithm Address for Primary Algorithm extended Query table (see Table 34.) Alternate Vendor Command Set and Control Interface ID Code second vendor - specified algorithm supported Address for Alternate Algorithm extended Query table p = 10Ah NA NA Query Unique ASCII String "QRY" Manufacturer Code Device Code Reserved Reserved Reserved "Q" "R" "Y" Description Value ST Top Bottom
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M30L0R7000T0, M30L0R7000B0
Table 33. CFI Query System Interface Information
Offset 01Bh Data 0017h Description VDD Logic Supply Minimum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts VDD Logic Supply Maximum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts VPP [Programming] Supply Minimum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 millivolts VPP [Programming] Supply Maximum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 millivolts Typical time-out per single byte/word program = 2n s Typical time-out for Buffer Program = 2n s Typical time-out per individual block erase = 2n ms Typical time-out for full chip erase = 2n ms Maximum time-out for word program = 2n times typical Maximum time-out for Buffer Program = 2n times typical Maximum time-out per individual block erase = 2n times typical Maximum time-out for chip erase = 2n times typical Value 1.7V
01Ch
0020h
2V
01Dh
0085h
8.5V
01Eh 01Fh 020h 021h 022h 023h 024h 025h 026h
0095h 0004h 0009h 000Bh 0000h 0003h 0001h 0001h 0000h
9.5V 16s 512s 2s NA 128s 1024s 4s NA
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M30L0R7000T0, M30L0R7000B0
Table 34. Device Geometry Definition
Offset Word Mode 027h 028h 029h 02Ah 02Bh 02Ch 02Dh 02Eh M30L0R7000T0 02Fh 030h 031h 032h 033h 034h 035h 038h 02Dh 02Eh M30L0R7000B0 02Fh 030h 031h 032h 033h 034h 035h 038h Data 0018h 0001h 0000h 0006h 0000h 0002h 007Eh 0000h 0000h 0002h 0003h 0000h 0080h 0000h Reserved 0003h 0000h 0080h 0000h 007Eh 0000h 0000h 0002h Reserved Description Device Size = 2n in number of bytes Flash Device Interface Code description Maximum number of bytes in multi-byte program or page = 2n Number of identical sized erase block regions within the device bit 7 to 0 = x = number of Erase Block Regions Region 1 Information Number of identical-size erase blocks = 007Eh+1 Region 1 Information Block size in Region 1 = 0200h * 256 Byte Region 2 Information Number of identical-size erase blocks = 0003h+1 Region 2 Information Block size in Region 2 = 0080h * 256 Byte Reserved for future erase block region information Region 1 Information Number of identical-size erase block = 0003h+1 Region 1 Information Block size in Region 1 = 0080h * 256 bytes Region 2 Information Number of identical-size erase block = 007Eh+1 Region 2 Information Block size in Region 2 = 0200h * 256 bytes Reserved for future erase block region information Value 16 MBytes x16 Async. 64 Bytes 2 127 128 KByte 4 32 KByte NA 4 32 KBytes 127 128 KBytes NA
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M30L0R7000T0, M30L0R7000B0
Table 35. Primary Algorithm-Specific Extended Query Table
Offset (P)h = 10Ah Data 0050h 0052h 0049h (P+3)h = 10Dh (P+4)h = 10Eh (P+5)h = 10Fh 0031h 0033h 00E6h 0003h (P+7)h = 111h (P+8)h = 112h 0000h 0000h Major version number, ASCII Minor version number, ASCII Extended Query table contents for Primary Algorithm. Address (P+5)h contains less significant byte. bit 0 Chip Erase supported (1 = Yes, 0 = No) bit 1 Erase Suspend supported (1 = Yes, 0 = No) bit 2 Program Suspend supported (1 = Yes, 0 = No) bit 3 Legacy Lock/Unlock supported (1 = Yes, 0 = No) bit 4 Queued Erase supported (1 = Yes, 0 = No) bit 5 Instant individual block locking supported (1 = Yes, 0 = No) bit 6 Protection bits supported (1 = Yes, 0 = No) bit 7 Page mode read supported (1 = Yes, 0 = No) bit 8 Synchronous read supported (1 = Yes, 0 = No) bit 9 Simultaneous operation supported (1 = Yes, 0 = No) bit 10 to 31Reserved; undefined bits are `0'. If bit 31 is '1' then another 31 bit field of optional features follows at the end of the bit-30 field. Supported Functions after Suspend Read Array, Read Status Register and CFI Query Yes bit 0 bit 7 to 1 (P+A)h = 114h (P+B)h = 115h 0003h 0000h Program supported after Erase Suspend (1 = Yes, 0 = No) Reserved; undefined bits are `0' No Yes Yes No No Yes Yes Yes Yes Yes Primary Algorithm extended Query table unique ASCII string "PRI" Description Value "P" "R" "I" "1" "3"
(P+9)h = 113h
0001h
Block Protect Status Defines which bits in the Block Status Register section of the Query are implemented. bit 0 Block protect Status Register Lock/Unlock bit active (1 = Yes, 0 = No) bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No) bit 15 to 2 Reserved for future use; undefined bits are `0' VDD Logic Supply Optimum Program/Erase voltage (highest performance)
Yes Yes
(P+C)h = 116h
0018h
bit 7 to 4 bit 3 to 0
HEX value in volts BCD value in 100 mV
1.8V
VPP Supply Optimum Program/Erase voltage (P+D)h = 117h 0090h bit 7 to 4 bit 3 to 0 HEX value in volts BCD value in 100 mV 9V
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Table 36. Protection Register Information
Offset (P+E)h = 118h (P+F)h = 119h (P+10)h = 11Ah (P+11)h = 11Bh (P+12)h = 11Ch (P+13)h = 11Dh (P+14)h = 11Eh (P+15)h = 11Fh (P+16)h = 120h (P+17)h = 121h (P+18)h = 122h (P+19)h = 123h (P+1A)h = 124h (P+1B)h = 125h (P+1C)h = 126h Data 0002h 0080h 0000h 0003h 0003h 0089h 0000h 0000h 0000h 0000h 0000h 0000h 0010h 0000h 0004h Description Number of protection register fields in JEDEC ID space. 0000h indicates that 256 fields are available. Protection Field 1: Protection Description Bits 0-7 Lower byte of protection register address Bits 8-15 Upper byte of protection register address Bits 16-23 2n bytes in factory pre-programmed region Bits 24-31 2n bytes in user programmable region Protection Register 2: Protection Description Bits 0-31 protection register address Bits 32-39 n number of factory programmed regions (lower byte) Bits 40-47 n number of factory programmed regions (upper byte) Bits 48-55 2n bytes in factory programmable region Bits 56-63 n number of user programmable regions (lower byte) Bits 64-71 n number of user programmable regions (upper byte) Bits 72-79 2n bytes in user programmable region Value 2 80h 00h 8 Bytes 8 Bytes 89h 00h 00h 00h 0 0 0 16 0 16
Table 37. Burst Read Information
Offset (P+1D)h = 127h Data 0003h Description Page-mode read capability bits 0-7 'n' such that 2n HEX value represents the number of readpage bytes. See offset 28h for device word width to determine page-mode data output width. Number of synchronous mode read configuration fields that follow. Synchronous mode read capability configuration 1 bit 3-7 Reserved bit 0-2 'n' such that 2n+1 HEX value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. A value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the device's burstable address space. This field's 3-bit value can be written directly to the read configuration register bit 0-2 if the device is configured for its maximum word width. See offset 28h for word width to determine the burst data output width. Synchronous mode read capability configuration 2 Synchronous mode read capability configuration 3 Synchronous mode read capability configuration 4 Value 8 Bytes
(P+1E)h = 128h (P+1F)h = 129h
0004h 0001h
4 4
(P+20)h = 12Ah (P-21)h = 12Bh (P+22)h = 12Ch
0002h 0003h 0007h
8 16 Cont.
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Table 38. Bank and Erase Block Region Information
Flash memory (top) Offset (P+23)h = 12Dh Data 02h Flash memory (bottom) Description Offset (P+23)h = 12Dh Data 02h Number of Bank Regions within the device
Note: 1. The variable P is a pointer which is defined at CFI offset 15h. 2. Bank Regions. There are two Bank Regions, see Table 29. and Table 30.
Table 39. Bank and Erase Block Region 1 Information
Flash memory (top) Offset (P+24)h = 12Eh (P+25)h = 12Fh Data 0Fh 00h Flash memory (bottom) Description Offset (P+24)h = 12Eh (P+25)h = 12Fh Data 01h 00h Number of program or erase operations allowed in Bank Region 1: Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Number of program or erase operations allowed in other banks while a bank in same region is programming Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Number of program or erase operations allowed in other banks while a bank in this region is erasing Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Types of erase block regions in Bank Region 1 n = number of erase block regions with contiguous same-size erase blocks. Symmetrically blocked banks have one blocking region(2). Number of identical banks within Bank Region 1
(P+26)h = 130h
11h
(P+26)h = 130h
11h
(P+27)h = 131h
00h
(P+27)h = 131h
00h
(P+28)h = 132h
00h
(P+28)h = 132h
00h
(P+29)h = 133h
01h
(P+29)h = 133h
02h
(P+2A)h = 134h (P+2B)h = 135h (P+2C)h = 136h (P+2D)h = 137h (P+2E)h = 138h (P+2F)h = 139h
77h 00h 00h 02h 64h 00h
(P+2A)h = 134h (P+2B)h = 135h (P+2C)h = 136h (P+2D)h = 137h (P+2E)h = 138h (P+2F)h = 139h
03h 00h 80h 00h 64h 00h Bank Region 1 (Erase Block Type 1) Minimum block erase cycles x 1000 Bank Region 1 (Erase Block Type 1): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for "internal ECC used" BIts 5-7: reserved Bank Region 1 (Erase Block Type 1): Page mode and Synchronous mode capabilities Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved Bank Region 1 Erase Block Type 1 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: nx256 = number of bytes in erase block region
(P+30)h = 13Ah
02h
(P+30)h = 13Ah
02h
(P+31)h = 13Bh
03h
(P+31)h = 13Bh
03h
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M30L0R7000T0, M30L0R7000B0
Flash memory (top) Offset Data Flash memory (bottom) Description Offset (P+32)h = 13Ch (P+33)h = 13Dh (P+34)h = 13Eh (P+35)h = 13Fh (P+36)h = 140h (P+37)h = 141h Data 06h 00h 00h 02h 64h 00h Bank Region 1 (Erase Block Type 2) Minimum block erase cycles x 1000 Bank Regions 1 (Erase Block Type 2): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for "internal ECC used" BIts 5-7: reserved Bank Region 1 (Erase Block Type 2): Page mode and Synchronous mode capabilities Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved Bank Region 1 Erase Block Type 2 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: nx256 = number of bytes in erase block region
(P+38)h = 142h
02h
(P+39)h = 143h
03h
Note: 1. The variable P is a pointer which is defined at CFI offset 15h. 2. Bank Regions. There are two Bank Regions, There are two Bank Regions, see Table 29. and Table 30.
Table 40. Bank and Erase Block Region 2 Information
Flash memory (top) Offset (P+32)h = 13Ch (P+33)h = 13Dh Data 01h 00h Flash memory (bottom) Description Offset (P+3A)h = 144h (P+3B)h = 145h Data 0Fh Number of identical banks within Bank Region 2 00h Number of program or erase operations allowed in Bank Region 2: Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Number of program or erase operations allowed in other banks while a bank in this region is programming Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Number of program or erase operations allowed in other banks while a bank in this region is erasing Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Types of erase block regions in Bank Region 2 n = number of erase block regions with contiguous same-size erase blocks. Symmetrically blocked banks have one blocking region.(2)
(P+34)h = 13Eh
11h
(P+3C)h = 146h
11h
(P+35)h = 13Fh
00h
(P+3D)h = 147h
00h
(P+36)h = 140h
00h
(P+3E)h = 148h
00h
(P+37)h = 141h
02h
(P+3F)h = 149h
01h
(P+38)h = 142h (P+39)h = 143h (P+3A)h = 144h (P+3B)h = 145h
06h 00h 00h 02h
(P+40)h = 14Ah (P+41)h = 14Bh (P+42)h = 14Ch (P+43)h = 14Dh
77h 00h 00h 02h Bank Region 2 Erase Block Type 1 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: nx256 = number of bytes in erase block region
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Flash memory (top) Offset (P+3C)h = 146h (P+3D)h = 147h Data 64h 00h Flash memory (bottom) Description Offset (P+44)h = 14Eh (P+45)h = 14Fh Data 64h 00h Bank Region 2 (Erase Block Type 1) Minimum block erase cycles x 1000 Bank Region 2 (Erase Block Type 1): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for "internal ECC used" BIts 5-7: reserved Bank Region 2 (Erase Block Type 1):Page mode and Synchronous mode capabilities (defined in Table 37.) Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved
(P+3E)h = 148h
02h
(P+46)h = 150h
02h
(P+3F)h = 149h
03h
(P+47)h = 151h
03h
(P+40)h = 14Ah (P+41)h = 14Bh (P+42)h = 14Ch (P+43)h = 14Dh (P+44)h =14Eh (P+45)h = 14Fh
03h 00h 80h 00h 64h 00h Bank Region 2 (Erase Block Type 2) Minimum block erase cycles x 1000 Bank Region 2 (Erase Block Type 2): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for "internal ECC used" BIts 5-7: reserved Bank Region 2 (Erase Block Type 2): Page mode and Synchronous mode capabilities (defined in Table 37.) Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved (P+48)h = 152h (P+43)h = 153h Feature Space definitions Reserved Bank Region 2 Erase Block Type 2 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: nx256 = number of bytes in erase block region
(P+46)h = 150h
02h
(P+47)h = 151h
03h
(P+48)h = 152h (P+49)h = 153h
Note: 1. The variable P is a pointer which is defined at CFI offset 15h. 2. Bank Regions. There are two Bank Regions, There are two Bank Regions, see Table 29. and Table 30.
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M30L0R7000T0, M30L0R7000B0
APPENDIX C. FLOWCHARTS AND PSEUDO CODES
Figure 22. Program Flowchart and Pseudo Code
Start program_command (addressToProgram, dataToProgram) {: Write 40h or 10h (3) writeToFlash (addressToProgram, 0x40); /*writeToFlash (addressToProgram, 0x10);*/ /*see note (3)*/ writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/ do { status_register=readFlash (addressToProgram); "see note (3)"; /* E or G must be toggled*/ NO } while (status_register.SR7== 0) ; YES SR3 = 0 YES SR4 = 0 YES SR1 = 0 YES End } NO Program to Protected Block Error (1, 2) if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ; NO Program Error (1, 2) if (status_register.SR4==1) /*program error */ error_handler ( ) ; NO VPP Invalid Error (1, 2) if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ;
Write Address & Data
Read Status Register (3)
SR7 = 1
AI06170b
Note: 1. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 3. Any address within the bank can equally be used.
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M30L0R7000T0, M30L0R7000B0
Figure 23. Buffer Program Flowchart and Pseudo Code
Buffer_Program_command (Start_Address, n, buffer_Program[] ) /* buffer_Program [] is an array structure used to store the address and data to be programmed to the Flash memory (the address must be within the segment Start Address and Start Address+n) */ { do {writeToFlash (Start_Address, 0xE8) ;
Start
Buffer Program E8h Command, Start Address Read Status Register
status_register=readFlash (Start_Address);
SR7 = 1 YES Write n(1), Start Address
NO
} while (status_register.SR7==0);
writeToFlash (Start_Address, n);
Write Buffer Data, Start Address
writeToFlash (buffer_Program[0].address, buffer_Program[0].data); /*buffer_Program[0].address is the start address*/
X=0
x = 0;
X=n NO
YES
while (xWrite Next Buffer Data, Next Program Address(2)
{ writeToFlash (buffer_Program[x+1].address, buffer_Program[x+1].data);
x++; X=X+1 } Program Buffer to Flash Confirm D0h
writeToFlash (Start_Address, 0xD0);
Read Status Register
do {status_register=readFlash (Start_Address);
SR7 = 1 YES Full Status Register Check(3)
NO
} while (status_register.SR7==0);
full_status_register_check(); }
End
AI08913b
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M30L0R7000T0, M30L0R7000B0
Figure 24. Program Suspend & Resume Flowchart and Pseudo Code
Start program_suspend_command ( ) { writeToFlash (any_address, 0xB0) ; writeToFlash (bank_address, 0x70) ; /* read status register to check if program has already completed */ Write 70h do { status_register=readFlash (bank_address) ; /* E or G must be toggled*/
Write B0h
Read Status Register
SR7 = 1 YES SR2 = 1
NO
} while (status_register.SR7== 0) ;
NO
Program Complete
if (status_register.SR2==0) /*program completed */ { writeToFlash (bank_address, 0xFF) ; read_data ( ) ; /*The device returns to Read Array (as if program/erase suspend was not issued).*/ } else { writeToFlash (bank_address, 0xFF) ;
Write FFh
YES Write FFh
Read Data
Read data from another address
read_data ( ); /*read data from another address*/
Write D0h
writeToFlash (any_address, 0xD0) ; /*write 0xD0 to resume program*/
Write 70h(1) } Program Continues with Bank in Read Status Register Mode }
writeToFlash (bank_address, 0x70) ; /*read status register to check if program has completed */
AI10117b
Note: The Read Status Register command (Write 70h) can be issued just before or just after the Program Resume command.
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M30L0R7000T0, M30L0R7000B0
Figure 25. Block Erase Flowchart and Pseudo Code
Start erase_command ( blockToErase ) { writeToFlash (blockToErase, 0x20) ; /*see note (2) */ writeToFlash (blockToErase, 0xD0) ; /* only A12-A22 are significant */ /* Memory enters read status state after the Erase Command */ do { status_register=readFlash (blockToErase) ; /* see note (2) */ /* E or G must be toggled*/
Write 20h (2)
Write Block Address & D0h
Read Status Register (2)
SR7 = 1
NO } while (status_register.SR7== 0) ;
YES SR3 = 0 YES SR4, SR5 = 1 NO SR5 = 0 YES SR1 = 0 YES End } NO Erase to Protected Block Error (1) if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ; NO Erase Error (1) if ( (status_register.SR5==1) ) /* erase error */ error_handler ( ) ; YES Command Sequence Error (1) if ( (status_register.SR4==1) && (status_register.SR5==1) ) /* command sequence error */ error_handler ( ) ; NO VPP Invalid Error (1) if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ;
AI10524
Note: 1. If an error is found, the Status Register must be cleared before further Program/Erase operations. 2. Any address within the bank can equally be used.
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Figure 26. Erase Suspend & Resume Flowchart and Pseudo Code
Start
Write B0h
erase_suspend_command ( ) { writeToFlash (bank_address, 0xB0) ; writeToFlash (bank_address, 0x70) ; /* read status register to check if erase has already completed */
Write 70h
Read Status Register
do { status_register=readFlash (bank_address) ; /* E or G must be toggled*/
SR7 = 1 YES SR6 = 1
NO
} while (status_register.SR7== 0) ;
NO
Erase Complete
if (status_register.SR6==0) /*erase completed */ { writeToFlash (bank_address, 0xFF) ;
Write FFh
Read Data YES Write FFh Read data from another block or Program/Protection Register Program or Block Lock/Unlock/Lock-Down Write D0h else }
read_data ( ) ; /*The device returns to Read Array (as if program/erase suspend was not issued).*/
{ writeToFlash (bank_address, 0xFF) ; read_program_data ( ); /*read or program data from another block*/
writeToFlash (bank_address, 0xD0) ; /*write 0xD0 to resume erase*/ writeToFlash (bank_address, 0x70) ; /*read status register to check if erase has completed */ } }
Write 70h(1)
Erase Continues with Bank in Read Status Register Mode
Note: The Read Status Register command (Write 70h) can be issued just before or just after the Erase Resume command.
AI10116b
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M30L0R7000T0, M30L0R7000B0
Figure 27. Locking Operations Flowchart and Pseudo Code
Start
Write 60h (1)
locking_operation_command (address, lock_operation) { writeToFlash (address, 0x60) ; /*configuration setup*/ /* see note (1) */ if (lock_operation==LOCK) /*to protect the block*/ writeToFlash (address, 0x01) ; else if (lock_operation==UNLOCK) /*to unprotect the block*/ writeToFlash (address, 0xD0) ; else if (lock_operation==LOCK-DOWN) /*to lock the block*/ writeToFlash (address, 0x2F) ; writeToFlash (address, 0x90) ; /*see note (1) */
Write 01h, D0h or 2Fh
Write 90h (1)
Read Block Lock States
Locking change confirmed? YES Write FFh (1)
NO
if (readFlash (address) ! = locking_state_expected) error_handler () ; /*Check the locking state (see Read Block Signature table )*/
writeToFlash (address, 0xFF) ; /*Reset to Read Array mode*/ /*see note (1) */ }
End
AI06176b
Note: 1. Any address within the bank can equally be used.
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Figure 28. Protection Register Program Flowchart and Pseudo Code
Start
Write C0h (3)
protection_register_program_command (addressToProgram, dataToProgram) {: writeToFlash (addressToProgram, 0xC0) ; /*see note (3) */ writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/ do { status_register=readFlash (addressToProgram) ; /* see note (3) */ /* E or G must be toggled*/ NO } while (status_register.SR7== 0) ;
Write Address & Data
Read Status Register (3)
SR7 = 1 YES SR3 = 0 YES SR4 = 0 YES SR1 = 0 YES End
NO
VPP Invalid Error (1, 2)
if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ;
NO
Program Error (1, 2)
if (status_register.SR4==1) /*program error */ error_handler ( ) ;
NO
Program to Protected Block Error (1, 2)
if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ;
}
AI06177b
Note: 1. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 3. Any address within the bank can equally be used.
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M30L0R7000T0, M30L0R7000B0
Figure 29. Buffer Enhanced Factory Program Flowchart and Pseudo Code
Start Write 80h to Address WA1 SETUP PHASE Buffer_Enhanced_Factory_Program_Command (start_address, DataFlow[]) { writeToFlash (start_address, 0x80) ;
Write D0h to Address WA1
writeToFlash (start_address, 0xD0) ; do{ do { status_register = readFlash (start_address);
Read Status Register
NO
SR7 = 0 YES
if (status_register.SR4==1) { /*error*/ if (status_register.SR3==1) /*VPP error */ error_handler ( ) ; if (status_register.SR1==1) /* Locked Block */ error_handler ( ) ; } while (status_register.SR7==1)
NO
SR4 = 1
Initialize count X=0 Write PDX Address WA1
PROGRAM AND VERIFY PHASE
Read Status Register SR3 and SR1for errors
x=0; /* initialize count */
Exit
Increment Count X=X+1
do { writeToFlash (start_address, DataFlow[x]); x++; }while (x<32) do { status_register = readFlash (start_address); }while (status_register.SR0==1)
NO
X = 32 YES Read Status Register
NO
SR0 = 0 YES
NO
Last data? YES Write FFFFh to Address = NOT WA1 } while (not last data)
writeToFlash (another_block_address, FFFFh)
Read Status Register
EXIT PHASE
do { status_register = readFlash (start_address)
NO
}while (status_register.SR7==0) SR7 = 1 YES Full Status Register Check End
AI07302B
full_status_register_check();
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APPENDIX D. COMMAND INTERFACE STATE TABLES
Table 41. Command Interface States - Modify Table, Next State
Block Erase, Setup
(3,4)
Current CI State
Read Program Buffer Setup Program Array(2) (3,4) (3,4) (FFh) (10/40h) (E8h) Buffer Program Program Setup Setup
Command Input Erase Confirm P/E Resume, BEFP Block Unlock Setup confirm, (80h) BEFP Confirm
(3,4)
(20h) Erase Setup BEFP Setup
(D0h) Ready Lock/CR Setup OTP Setup Busy Setup Busy Suspend Setup Buffer Load 1 Buffer Load 2 Program Busy Ready
Buffer Program, Program/ Erase Suspend (B0h)
Read Clear Electronic Read status Signature, Status Register Register Read CFI (5) (70h) Query (50h) (90h, 98h) Ready
Ready (Lock Error)
Ready (unlock block) OTP Busy Program Busy Program Suspend
Ready (Lock Error)
Program
Program Busy
Program Suspend Program Busy Program Suspend Buffer Program Load 1 (give word count load (N-1)); if N=0 go to Buffer Program Confirm. Else (N not =0) go to Buffer Program Load 2 (data load)
Buffer Program Confirm when count =0; Else Buffer Program Load 2 (note: Buffer Program will fail at this point if any block address is different from the first address) Buffer Buffer Program Ready (error) Ready (error) Program Confirm Busy Buffer Busy Buffer Program Busy Program Buffer Program Busy Suspend Buffer Program Buffer Program Suspend Suspend Buffer Program Suspend Busy Setup Ready (error) Erase Busy Ready (error) Erase Busy Erase Busy Erase Busy Suspend Buffer Erase Program Program Erase Suspend in Erase Setup in Erase Suspend Erase Busy Erase Suspend Suspend Erase Suspend Suspend Setup Program Busy in Erase Suspend Program Suspend in Program Busy in Erase Suspend Program Busy Program Busy in Erase Suspend Erase in Erase Suspend Suspend Program Busy Suspend Program Suspend in Erase Suspend in Erase Program Suspend in Erase Suspend Suspend
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M30L0R7000T0, M30L0R7000B0
Command Input Erase Confirm P/E Resume, BEFP Block Unlock Setup confirm, (80h) BEFP Confirm
(3,4)
Current CI State
Read Program Buffer Setup Program Array(2) (3,4) (3,4) (FFh) (10/40h) (E8h)
Block Erase, Setup
(3,4)
(20h)
Setup Buffer Load 1 Buffer Load 2 Buffer Program in Erase Suspend Confirm
(D0h) Buffer Program Load 1 in Erase Suspend (give word count load (N-1)); if N=0 go to Buffer Program confirm. Else (N not =0) go to Buffer Program Load 2 Buffer Program Load 2 in Erase Suspend (data load) Buffer Program Confirm in Erase Suspend when count =0; Else Buffer Program Load 2 in Erase Suspend (note: Buffer Program will fail at this point if any block address is different from the first address) Buffer Program Ready (error) Busy in Erase Ready (error) Suspend Buffer Program Buffer Program Busy in Erase Buffer Program Busy in Erase Suspend Suspend in Suspend Erase Suspend Buffer Program Buffer Program Suspend in Erase Suspend Busy in Erase Buffer Program Suspend in Erase Suspend Suspend Erase Suspend (Lock Error) Ready (error) Erase Suspend BEFP Busy BEFP Busy (6) Erase Suspend (Lock Error) Ready (error)
Buffer Program, Program/ Erase Suspend (B0h)
Read Clear Read Electronic status Signature, Status Register Register Read CFI (5) (70h) Query (50h) (90h, 98h)
Busy
Suspend Lock/CR Setup in Erase Suspend Setup Buffer EFP Busy
Note: 1. CI = Command Interface, CR = Configuration Register, BEFP = Buffer Enhanced Factory Program, P/E. C. = Program/Erase Controller. 2. At Power-Up, all banks are in Read Array mode. Issuing a Read Array command to a busy bank, results in undetermined data output. 3. The two cycle command should be issued to the same bank address. 4. If the P/E.C. is active, both cycles are ignored. 5. The Clear Status Register command clears the Status Register error bits except when the P/E.C. is busy or suspended. 6. BEFP is allowed only when Status Register bit SR0 is set to `0'. BEFP is busy if Block Address is first BEFP Address. Any other commands are treated as data.
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M30L0R7000T0, M30L0R7000B0
Table 42. Command Interface States - Modify Table, Next Output State
Command Input Erase Confirm P/E Resume, Program/ Read BEFP Block Status Erase Setup Unlock Suspend Register (80h) confirm, (70h) (B0h) BEFP Confirm
(4,5)
Current CI State
Read Program Buffer Array Setup Program (3) (4,5) (E8h) (FFh) (10/40h)
Block Erase, Setup
(4,5)
(20h)
Clear status Register (50h)
Read Electronic signature, Read CFI Query (90h, 98h)
(D0h) Program Setup Erase Setup OTP Setup Program in Erase Suspend BEFP Setup BEFP Busy Buffer Program Setup Buffer Program Load 1 Buffer Program Load 2 Buffer Program Confirm Buffer Program Setup in Erase Suspend Buffer Program Load 1 in Erase Suspend Buffer Program Load 2 in Erase Suspend Buffer Program Confirm in Erase Suspend Lock/CR Setup Lock/CR Setup in Erase Suspend OTP Busy
Status Register
Status Register
Ready Program Busy Erase Busy Buffer Program Busy Program/Erase Suspend Status Output Buffer Program Suspend Array Status Register Output Unchanged Register Unchanged Electronic Program Busy in Erase Signature/ Suspend CFI Buffer Program Busy in Erase Suspend Program Suspend in Erase Suspend Buffer Program Suspend in Erase Suspend Note: 1. The output state shows the type of data that appears at the outputs if the bank address is the same as the command address. A bank can be placed in Read Array, Read Status Register, Read Electronic Signature or Read CFI mode, depending on the command issued. Each bank remains in its last output state until a new command is issued to that bank. The next state does not depend on the bank output state. 2. CI = Command Interface, CR = Configuration Register, BEFP = Buffer Enhanced Factory Program, P/E. C. = Program/Erase Controller. 3. At Power-Up, all banks are in Read Array mode. Issuing a Read Array command to a busy bank, results in undetermined data output. 4. The two cycle command should be issued to the same bank address. 5. If the P/E.C. is active, both cycles are ignored.
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Table 43. Command Interface States - Lock Table, Next State
Command Input Current CI State Lock/CR Setup(2) (60h) Lock/CR Setup OTP Setup (2) (C0h) OTP Setup Ready OTP Busy Program Busy Program Busy Program Suspend Buffer Program Load 1 (give word count load (N-1)); Buffer Program Load 2(6) Exit see note (6) Block Block Lock Lock-Down Confirm Confirm (01h) (2Fh) Set CR Confirm (03h) Ready Ready (Lock error) Block Address (WA0) (3) (XXXXh) Illegal Command (5) WSM Operation Completed N/A N/A N/A Ready N/A Ready N/A N/A N/A N/A N/A Ready N/A N/A Ready
Ready Lock/CR Setup OTP Setup Busy Setup Program Busy Suspend Setup Buffer Load 1 Buffer Program Buffer Load 2 Confirm Busy Suspend Setup Busy Erase Suspend
Ready (Lock error)
Buffer Program Confirm when count =0; Else Buffer Program Load 2 (note: Buffer Program will fail at this point if any block address is different from the first address) Ready (error) Buffer Program Busy Buffer Program Suspend Ready (error) Erase Busy Lock/CR Setup in Erase Suspend
Erase Suspend
N/A
Setup Program in Erase Suspend Busy Suspend Setup Buffer Load 1 Buffer Program in Erase Suspend Buffer Load 2 Confirm Busy Suspend Lock/CR Setup in Erase Suspend Setup BEFP Busy
Program Busy in Erase Suspend Program Busy in Erase Suspend Program Suspend in Erase Suspend Buffer Program Load 1 in Erase Suspend (give word count load (N-1)) Buffer Program Load 2 in Erase Suspend(7) Exit see note (7)
N/A Erase Suspend
Buffer Program Confirm in Erase Suspend when count =0; Else Buffer Program Load 2 in Erase Suspend (note: Buffer Program will fail at this point if any block address is different from the first address) Ready (error) Buffer Program Busy in Erase Suspend Buffer Program Suspend in Erase Suspend Erase Suspend (Lock error) Erase Suspend Ready (error) BEFP Busy (4) Exit BEFP Busy(4) Erase Suspend (Lock error)
N/A
N/A N/A N/A
Note: 1. CI = Command Interface, CR = Configuration Register, BEFP = Buffer Enhanced Factory Program, P/E. C. = Program/Erase Controller, WA0 = Address in a block different from first BEFP address. 2. If the P/E.C. is active, both cycles are ignored. 3. BEFP Exit when Block Address is different from first Block Address and data are FFFFh. 4. BEFP is allowed only when Status Register bit SR0 is set to `0'. BEFP is busy if Block Address is first BEFP Address. Any other commands are treated as data. 5. Illegal commands are those not defined in the command set. 6. if N=0 go to Buffer Program Confirm. Else (N 0) go to Buffer Program Load 2 (data load). 7. if N=0 go to Buffer Program Confirm in Erase Suspend. Else (N 0) go to Buffer Program Load 2 in Erase Suspend.
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Table 44. Command Interface States - Lock Table, Next Output State
Current CI State Lock/CR Setup(3) (60h) OTP Setup(3) (C0h) Block Lock Confirm (01h) Command Input Block Set CR Lock-Down Confirm Confirm (03h) (2Fh) BEFP Exit(4) (FFFFh) Illegal Command
(5)
WSM Operation Completed
Program Setup Erase Setup OTP Setup Program in Erase Suspend BEFP Setup BEFP Busy Buffer Program Setup Buffer Program Load 1 Buffer Program Load 2 Buffer Program Confirm Buffer Program Setup in Erase Suspend Buffer Program Load 1 in Erase Suspend Buffer Program Load 2 in Erase Suspend Buffer Program Confirm in Erase Suspend Lock/CR Setup Lock/CR Setup in Erase Suspend OTP Busy Ready Program Busy Erase Busy Buffer Program Busy Program/Erase Suspend Buffer Program Suspend Program Busy in Erase Suspend Buffer Program Busy in Erase Suspend Program Suspend in Erase Suspend Buffer Program Suspend in Erase Suspend
Status Register
Output Unchanged
Status Register
Array
Status Register
Status Register
Output Unchanged
Array
Output Unchanged
Note: 1. The output state shows the type of data that appears at the outputs if the bank address is the same as the command address. A bank can be placed in Read Array, Read Status Register, Read Electronic Signature or Read CFI mode, depending on the command issued. Each bank remains in its last output state until a new command is issued to that bank. The next state does not depend on the bank's output state. 2. CI = Command Interface, CR = Configuration Register, BEFP = Buffer Enhanced Factory Program, P/E. C. = Program/Erase Controller, WA0 = Address in a block different from first BEFP address. 3. If the P/E.C. is active, both cycles are ignored. 4. BEFP Exit when Block Address is different from first Block Address and data are FFFFh. 5. Illegal commands are those not defined in the command set.
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M30L0R7000T0, M30L0R7000B0
REVISION HISTORY
Table 45. Document Revision History
Date 05-May-2003 Version 0.1 First Issue Write to Buffer and Program command renamed Buffer Program command. Clear Status Register Command, Set Configuration Register Command and Synchronous Burst Read Mode clarified. Table 15., Program, Erase Times and Endurance Cycles reformatted, and Buffer Enhanced Factory Program timings added. In Table 19., DC Characteristics - Currents, IDD1, IDD2, IDD3, IDD4, IDD6 and IDD7, values changed and 16 Word burst values added. VPP1 and VPPLK values modified in Table 20., DC Characteristics - Voltages. APPENDIX A., BLOCK ADDRESS TABLES reformatted. In APPENDIX B., COMMON FLASH INTERFACE, 0 added in front of 2-digit offset values. Data modified at address offset (P + 1D)h = 127h in Table 37., Burst Read Information. Figure 29., Buffer Enhanced Factory Program Flowchart and Pseudo Code modified. APPENDIX D., COMMAND INTERFACE STATE TABLES added. Figure 24., Program Suspend & Resume Flowchart and Pseudo Code, Figure 25., Block Erase Flowchart and Pseudo Code and Figure 26., Erase Suspend & Resume Flowchart and Pseudo Code modified. Flowchart modified and Pseudo code added to Figure 23., Buffer Program Flowchart and Pseudo Code. Small text changes. Alt symbol for tAVWH and tAVEH removed from Tables 23 and 24, respectively. TFBGA88 package fully compliant with the ST ECOPACK specification. Document status promoted from Target Specification to full Datasheet. Revision Details
17-Mar-2004
0.2
03-Dec-2004
1.0
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. ECOPACK is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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